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new to asic and need help

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tarek1984

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hello

i have a digital design which is done and running on fpga now i want to move to asic but i do not know where to start .what tools i can use
i am a master student so if anybody can suggest me what tools i can start with


please do not make your answer just about the diffrance between fpga and asic and the diffrant design steps because i know that
i want to know what tools are the best for my as a student


thanks
 

yx.yang

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modelsim or ncverilog for simulation.
Design Compiler (DC) for synthesis.
Astro or Encounter for Layout.
While I don't think you can use these tools well in a short time, even some ASIC design engineer with 2-3 years experience can't claim they have know these skill very well.
 

YuLongHuang

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Like yx.yang said. The standard design flow for ASIC is to write RTL first and then synthesis. The synthesis tool is like Synopsys Design Compiler. After this, you have to insert scan chain for test application. This is also done by DC. Next, P&R can be finished by Cadence SoC Encounter. Finally, DRC and LVS check should by applied before taped out.

PoLo
 

welcome2colours

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could u just tell me difference betwen simulation and synthesis
 

hari151087

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YuLongHuang
and we need to use prime time to dump sdc files
which are inputs to Encounter or Synopsyis Tool

---------- Post added 09-02-11 at 00:01 ---------- Previous post was 08-02-11 at 23:54 ----------

step 1: netlist which u hav

step 2: convert that Netlist to synthesised Netlist using DC
( This step is necessary in order to match with particular technology libraries)

step 3: next dump sdc for the synthesised Netlist using PrimeTime

step 4: give this synthesised netlist , sdc to encounter for further steps
floorplan, placement, CTS ,Routing, Timing Closure
You can use different tools for different steps
floorplan : encounter
placement : IC synopsys
power : sierra pinnacle
CTS : encounter
CTS opt : sierra pinnacle
route : nano route encounter

NOTE : for starters we can do single flow in encounter
 

phoenixpavan

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@ welcometocolours

Simulation -- Verification of your design for functional correctness
Synthesis -- Conversion of your HDL code to gate-level netlist

@tarek1984

You need to take your RTL code(I take it that it is functionally correct as it is working on a FPGA) for synthesis using the tool Design Compiler
From design compiler you have to use IC compiler or SOC Encounter for running it through the physical implementation steps(PnR)
For Timing closure you need to use Primetime
For Physical Verification you need to use Calibre

Regarding how to work with these tools....first you need access to these tools(plz chk with your university/college regarding their availabality).
If you have access to these tools all the tools mentioned above have their userguides posted in the forum somewhere couple of the threads are
https://www.edaboard.com/threads/12589/


So those userguides will be your starting points for exporting your design to ASIC

All the Best..
 

sunjianhuigou

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give some ideas about the diffrences bettween fpga and asic :
[1] : the resource -> (especially to the fpga realization), u need to consider the resources that the fpga chip can use(eg: FFS/Memory bits/adder/multiplier/pll), so u need to be carefull of the number of the above resources your coding will occupy when after mapping to the fpga chip.
[2]: the frequency -> the most frequency value that the fpga chip supportted is fixed,as the fpga chip is composed of the basic cell ,of course the clock network(composed of the special CLK-BUF belonging to the fpga). The physical characters of the CLK-BUF and the ALU which containing FF/Latch are fixed too, so the timing requierment is relatively fixed versus to the asic) , and the verilog/vhdl mapping is based on the constrained physical characters of the fpga. So using the fpga ,you should using the pll resource fully. Of couser you should be clear about the clock/reset structure,eg, sync/async, for asic,the clock structure is very important at the synthesis step, eg, false path setting bettween async clock zones (have no datapath for function ), fast clock lauch&slow clock capture and versus,clock generation, etc. But for fpga you can change your clock structure at anytime if you want,and debug your coding with chipscope/signaltap,as fpga support erase so many times, but asic is more difficult , the clock/reset structure is vital to the following P&R step(eg,CTS), and directly affect the most frequency value, time closure,etc.
[3]:why using fpga at the asic chip design?-> in order to evaluate the structure of the system and algorithm through the asic project steps,u need to using the fpga platflorm to quickly watch the result, it's the reason why using the fpga for the asic design.
[4]:the tools of fpga VS asic design->fpga: matlap(simulink xxx.m)->ise/quartus/nios2-H/W configuaration (verilog/vhdl coding, simulation,cpu hardware/software configuration, and translate/physical mapping is realized automatically, normally u dont need so hard to change the sdc constrain like the asic design, of course u can constrain the resource mapping)->chipscope/signaltap->finished! For asic ,you just have one chance, after tape-out, everything is over! C/C plusplus/SystemC help to setup the basic structure of the top module -> Simulation(NCverilog,so many tools...)->Synthesis(DC/RC,u clock tructure now is so important,and you should write sdc file accordingly)->formality(LEC/FORMALITY, circuit equality using some model and algorithm replaced simulation which cost much more time) -> P&R(SE/ICC)->LVS/DRC(SE/ICC/CALIBER),of cource u need care about the COST/AREA/SPEED/POWER/TIME2MARKET respects(which is most important o u?u should be clear at the chip planning period), during these processes,there are so many tools,tools is not the most important,you can study the Synopsys/Cadence/Mentor/Magama's tools and other tools from diffrent companys. Rootly , tool is mostly the same bettwen different companys ,just need to control one is enough.
[5] for asic design, u need to consider the lower power technic more hardly versus for fpga. Low power is the trend for the current soc chip design.
[6] fpga give you many chances to change your fault, but asic design you have no chance otherwise u don't konw where to spend your money.
 
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