dha_synth
Junior Member level 1
hello all,
This might be a silly question but it really made my concepts struggling.
We know conversion from rtl to gate level netlist or mapping of the rtl logic with library cells are done at the synthesis time but, we also cannot perform elaboration of the design reading library file.
elaboration involves in symantics checks and expanding of the top and its referances also data structure building.
My question is why elaboration step needs technology lib files ??
Thanks in advance
DHA_SYNTH
This might be a silly question but it really made my concepts struggling.
We know conversion from rtl to gate level netlist or mapping of the rtl logic with library cells are done at the synthesis time but, we also cannot perform elaboration of the design reading library file.
elaboration involves in symantics checks and expanding of the top and its referances also data structure building.
My question is why elaboration step needs technology lib files ??
Thanks in advance
DHA_SYNTH