# [moved] RTL Compiler, elaboration command

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#### dha_synth

##### Junior Member level 1
hello all,

This might be a silly question but it really made my concepts struggling.

We know conversion from rtl to gate level netlist or mapping of the rtl logic with library cells are done at the synthesis time but, we also cannot perform elaboration of the design reading library file.

elaboration involves in symantics checks and expanding of the top and its referances also data structure building.

My question is why elaboration step needs technology lib files ??

DHA_SYNTH

#### dpaul

Re: RTL Compiler, elaboration command

My question is why elaboration step needs technology lib files ??
DHA_SYNTH
The technology file defines layers and devices that are available for a particular fabrication process. The layer, physical, and electrical rules for the technology are also contained in the technology file.

So when you are doing elaboration, the tech lib files are used by the tool to present to the user the maximum level of permitted details.

#### dha_synth

##### Junior Member level 1
Re: RTL Compiler, elaboration command

as far as i am concirned after elaboration tool only informs about the usable logics and the usable sequential logics of the li-cells.

I am not getting what kind of permitted details you are talking about.

#### dpaul

I must say that I did not fully understand your question the last time and I might have also answered your question incorrectly. I have re-considered it and have the following.

First of you must understand that the elaboration step is a sub-process leading to the final synthesis. You cannot separate elaborate and synthesis.

Having said that, the following is what happens during the elaboration process:
Elaboration involves various design checking and optimizations and is a necessary step to proceed with synthesis. The elaborate command automatically elaborates the top-level design and all of its references. During elaboration, RTL Compiler performs the following tasks:
1. Builds data structures
2. Infers registers in the design
3. Performs higher-level HDL optimization, such as dead code removal
4. Checks semantics
At the end of elaboration, RTL Compiler displays any unresolved references (immediately after the key words Done elaborating):
Done elaborating '<top_level_module_name>'.
Cannot resolve reference to <ref01>
Cannot resolve reference to <ref02>
Cannot resolve reference to <ref03>
...

After elaboration, RTL Compiler has an internally created a data structure for the whole design so you can apply constraints and perform other operations.

Now the question is why technology library files need to be specified, right?
In real-world designs there are macros within a top-level design which are not defined by RTL (typical e.g. is a memory macro). Assume that a top.v file, has an instance of a module 'sub', but the top.v file does not contain a description of module 'sub'. After top.v is parsed, the elaborate command looks for undefined modules, such as 'sub', in the directories specified through the -libpath option. In such library paths the tech. libs. are mentioned. Thus the reading in of tech. lib. files becomes necessary where definitions of such undefined modules are "most likely" to exist. This also justifies why synthesis scripts contain search paths and library paths.

I might have answered what you are looking for and have mentioned whatever I knew about it, don't have a lot of experience with synthesis. I would recommend you read the Cadence "rc_user.pdf" manual or the other RC manuals if you want to have in-depth understanding. They are very informative and can answer most of your questions.

dha_synth

### dha_synth

Points: 2

#### dha_synth

##### Junior Member level 1
hello dpaul,

I got ur point of of including .lib for macros but, i have tried to elaborate a simple full adder which do not contain any macro or other things. The rc still shows the error of not including any library.
As written by you,

during elaboration,RTL Compiler performs the following tasks:
1. Builds data structures
2. Infers registers in the design
3. Performs higher-level HDL optimization, such as dead code removal
4. Checks semantics

all the above four points do not include any need of the technology library but still required..!!!, why is it so?
I hope you got my question now.

#### dpaul

Now you are coming to the real-world......could you post the exact error RC is reporting?
Also include all the commands you are using.

#### dha_synth

##### Junior Member level 1
Error : Failed to execute command. [LBR-116] [elaborate]
: No target technology library was loaded.
: Set the root 'library' attribute to a (list of) library name(s).

and i am using this commands, previously i have included search path for library and hdl

########################################################

#set_attribute library $LIBRARY / read_hdl$FILE_LIST
elaborate \$DESIGN

timestat Elaboration

check_design -unresolved
####################################

#### dpaul

The picture is now better!
But how can you proceed with synthesis without mentioning any library? Why did you remove the library paths in the TCL script?

Synthesis translates your RTL logic to gate-level netlist and in order to do that some library information is required.
The tech. libs. contains information on basic gates. RC uses this lib info to, say, break down a flop into a combination of basic gates. So libs. are required not only by undefined macros in your design but also by the RTL part of your design so that a gate level netlist is output.

A piece of advice for debugging: Did you try running each command in a RC instead of running whole script? In that way can pin point which command is creating the problem.

#### dha_synth

##### Junior Member level 1
Dear dpaul,

i do not have any problem in running this process, i was trying to figure out the case of elaboration without using lib. and i know the importance of lib in the synthesis very well

i am trying to run these commands one by one .

i just want to know the relation of elaboration step with the technology file.

#### dpaul

I really don't know how to give a more clear explanation.
My reply in #4 regarding 'elaboration' was taken from the Cadence "rc_user.pdf" manual.

But since in #5 you mentioned that you are having problems in synth a simple adder having no special macros and stuff, so I thought the problem might be somewhere else. That's why I asked you to include the TCL script and the errors.

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