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[Moved] Pipelined ADC (4-bit)

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musclesinwood

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Hi

I am designing a 4-bit pipelined ADC. First I did the system modeling and got an SNR of 24 dB. Then I did the transistor level design.
The problem I am having is in the distortion. In my Spectrum I am having distortion terms which I want to reduce. Any suggestions of how can I reduce distortion in the output spectrum of my ADC.

thank you
 

kemiyun

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Well, if you ask it this way, then my advice is: design a better ADC :D.

Please give more details, like where do you think this is coming from and general info on your architecture. Otherwise there would be no one who can help you with what is given in your question. Therefore we are wasting server space, let's put those bits to work :D.
 
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