After DC synthesis, logical shift went wrong, lost bit[0].

[ConfusedAlways]

Hello, Im new to asic, and i encountered a strange case in using logical shift.
In my RTL, I had the left logical shift to make the var 2 times multiplied. During the simulation, the results are good. Once the sythesis had finished, the LSB of 'fine_even' became high z. Meanwhile 'fine_odd' did the same operation, but its result is correct.
At the beginning I set the width the same which is 8bit, i think maybe after shifting it was enlarged one bit. So I changed it to 7bit and 8bit, sadly the results are the same as the former one.
Related code and waveforms are attached below. Hope someone could help me with it. Thanks in advance.

    reg [7:0] fine_odd;
    wire [6:0] out_odd_1;
    reg [7:0] fine_even;
    wire [6:0] out_even_1;  
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)begin
            fine_odd <= 'd0;
            fine_even <= 'd0;
        end else if (res_val_r)begin
            fine_even <= ((out_even_1 -1) << 1);
            fine_odd <= ((out_odd_1 -1) << 1) + 1;
        end else begin
            fine_even <= 'd0;
            fine_odd <= 'd0;
        end
    end

 

[ThisIsNotSam]

If I understood correctly, the last bit of fine_even is always zero, so it got automatically removed from your code. You could have an array with 1000 elements in there, it would make no difference. Always zero.

If you check your synthesis log, it is probably being mentioned in there that one bit is constant zero.

 

[ConfusedAlways]

If I understood correctly, the last bit of fine_even is always zero, so it got automatically removed from your code. You could have an array with 1000 elements in there, it would make no difference. Always zero.

If you check your synthesis log, it is probably being mentioned in there that one bit is constant zero.

Thanks for reply. Log mentioned this bit is a constant will be removed. Is it ok for me to set false these two 'compile_seqmap_propagate_constants' 'compile_delete_unloaded_sequential_cells' to solve the problem?

 

[ThisIsNotSam]

there is no problem to solve, this behavior is correct. the tool is saving power and area for you.

 

[ConfusedAlways]

there is no problem to solve, this behavior is correct. the tool is saving power and area for you.

It sure did. But losing the bit[0] would make the whole design not functioning properly, so I finally had it solved by adding those 2 commands. Thanks anyway!

--- Updated Mar 30, 2023 ---

there is no problem to solve, this behavior is correct. the tool is saving power and area for you.

I reviewed the synthesised results, and found the next stage logic using fine_even has a little problem, which makes the tool think fine_even wont be used, so it had the constant bit removed. You are right, I should not try to solve the problem in TOOLS.