[moved] Design compiler combinational circuits optimization

[Jecarusa]

Hello, I have a question, I am a newbie in using the design compiler. But I'm not sure if there is any way in .tcl scripts to optimize power circuits that don't use a clock, for example, an arithmetic circuit, a Ripple Carry Adder that only responds to its A and B inputs to give S as output. In area, set_max_area 0 can be used and i think it has an influence in power, but in power directly, does it only work for clock-dependent circuits?

 

[dpaul]

Please repost this to the ASIC Design sub-forum. maybe someone with extensive DC knowledge can answer this!

 

[oratie]

Create virtual clock, define set_input/output_delay regarding to this clock and go ahead...