Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Modified MCML logic for reducing the threshold voltage effect

Status
Not open for further replies.

hjzs18

Junior Member level 3
Joined
Dec 8, 2005
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,506
HI, all:
I am now studying MCML logic , and since the threshold voltage of the diff pair may impair the porformance of the the logic, i want to reduce the effect by using the topology below, i simulated this circuit and found it is really better than the one without using the two feedback transistors, but as i am not unable to reduce what is happening there, i think maybe you can help me find the transfer function of this circuit,

thanks a lot
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top