Simulate signal under noise effect in SystemVerilog

[quocviet19501]

Hi everyone, thank you for reading my post.
I'm doing a project in SystemVerilog and came across this problem.

In the above figure, I want to simulate a signal that has 2 unstable edges (effect of noise in real-time environment). But I have no idea how to make the 2 edges of data unstable. I have tried some methods, but they did not work.
Can anyone suggest some ideas?
Thank you.

 

[FvM]

Delay statement with variable delay using random function.

 

[quocviet19501]

Delay statement with variable delay using random function.

Thank you for your reply.
Could you explain some more and perhaps, provide an example. I don't really catch that.

 

[ThisIsNotSam]

systemverilog is good for RTL description, not for low-level timing effects.
what you are describing sounds more like an electrical level modelling that could be done with SPICE.

 

[dave_59]

It depends on what you are trying to functionally verify with this information. You certainly could use the X state to represent instability.

 

[D.A.(Tony)Stewart]

Both Data and clock need to be delayed up to 50% so the both data or clock can be controlled early and late to find the phase margin due to asymmetric delays, transition times and noise.

Back in my hardware days in the mid-80s window margin was measured with digital control in nanoseconds. There were several versions of digital phase margin analyzers which were very useful. One box could inject jitter on the data using a PRSG selected early, nominal and late into a system to check if the clock recovery had enough phase margin when the data also had bit shift in magnetic media.