memory element: latches and flip-flops

[aifi]

flops latches preferred

hi all...
according to my basic understanding, latches are level sensitive element and flip-flops are edge sensitive.. is it ok to use both in our design?

 

[rsrinivas]

it's preferable to avoid latches as they can ruin a design.

 

[deepa]

well careful design can infact make latch design more faster than flip flops,most of the amd processors use the technique of slack passing n borrowing ,which can be done in latch based design

 

[anishrai]

Its better to avoid latches.....flips flops are preferred

 

[dBUGGER]

Timing analysis becomes a lot more difficult with latches in your desin. Try to use FF's as much as possible. Your design will be much cleaner.

 

[aifi]

so, any idea to avoid latches in our design? it is apparent that the latch is because of our verilog code.

 

[rsrinivas]

if(not if - else) constructs and incomplete case statements synthesize to latches so avoid tem,pls do let me know if any other constructs wich synthesize to latches

 

[aifi]

'for loop' aslo can cause latch ..

example:

for(k=7;k>=0;k=k-1)
begin:flow
if(!copy_enable[k])
disable flow;
else
data_out[k] =data_in[k];
end

latch avoidence:

data_out = 8'b0;
for(k=7;k>=0;k=k-1)
begin:flow
if(!copy_enable[k])
disable flow;
else
data_out[k] =data_in[k];
end

 

[bharat_in]

hi deepa,
can you explain which kind of care one should take while using latches in design, in order to make it faster?

 

[alpeshchokshi]

latches r level sensitive
and with the help of 2 latch u can build one ff ...which is edge sensitive

 

[V]

But when to use Latch and when to use flip flop.....which are all deciding factors....

 

[shivakumar043]

if you use latches it creates problems while doing dft

 

[vinod_g]

flipflops are preferred compare to latches when testing.So,always use flipflops

 

[blanket]

If you care for performance (as is with microprocessors) latch is the best way. You don't idle your resource when it's possible to keep it cranking with data. However, the extraneous penalty you pay with a latch design is higher. What i mean is the effect of setup/skew is higher (not double) in latch based designs.

-b

 

[zhangpengyu]

mostly flip-flop is used.
but for power saving or cost down(area) ,latch may be used.
for example,using gated clock to do power saving.
use latch in datapath to reduce area.

 

[anilkumarv]

It is better to avoid latch in a design because it may cause some problems in timing ananlysis and dft.

 

[spauls]

Latch you can use for clock gating and clock generation,
Rest of the design you can use with FF.
By some special techniques you can do timing analysis and DFT of mixed latch and FF based designs.