Here is some info on CAD Tools that are used in IC design.
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Verilog Simulators
- VCS (Synopsys)
- NCVerilog (Cadence)
Synthesis
- DC - Design Compiler (Synopsys)
- RC - RTL compiler (Cadence)
gate level STA
- Primetime (Synopsys)
Transistor Level STA
- Nanotime (Synopsys)
Equivalency Checking
- Conformal LEC (Cadence) (thru Verplex Aquisition)
- Formality (Synopsys)
Equivalency Checking for SRAMs/Register Files (Memories)
- ESP-CV (Synopsys) (thru Innologic Aquisition)
ATPG (Automatic Test Pattern Generator)
- Fastscan (Mentor)
- Tetramax (Synopsys)
- Encounter Test (Cadence)
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some more CAD Tools ....
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Placement (P in P&R)
- IC compiler (Synopsys)
Routing (R in P&R)
- Astro , Zroute (Synopsys)
- Nanoroute (Cadence)
Physical Design Verification (PDV) ( LVS , DRC , ...)
- Calibre (Mentor)
- Assura (Cadence)
RC Extraction
- Star RC (Synopsys)
- Assura (Cadence)
Schematic Entry/Layout Design (Custom Tools)
- Virtuoso Schematic entry , Layout XL/VXL (Cadence)
Spice
- Hspice (Synopsys)
- Spectre (Cadence)
- Smartspice (Silvaco/Simucad)
Fast Spice
- Nanosim (Synopsys)
- Ultrasim (Cadence)
Power Estimation
- PrimePower (Synopsys)
- Powermeter (Cadence)
Library Characterization
- Signal Storm (Cadence)
- Liberty NCX (Synopsys)
EM/IR
- Voltagestorm (IR) , Electronstorm(EM) (Cadence)
- PrimeRail (Synopsys)
- Redhawk (Apache)
Property checking FV tools
- Magellan (Synopsys)
- Oin (Mentor)
- JasperGold (Jasper)
Test Compression
- TestKompress (Mentor)
- DFTMax compression (Synopsys)
- Encounter Testcompression (Cadence)
FPGA tools
- synplicity Tools (aquired by Synopsys)
PCB tools
- Allegro (Cadence)
IP portfolio
- Designware (Synopsys)
- Openchoice (Cadence)
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