max transition violation in soc enounter

[vlsitechnology]

How to resolve max transition violation related to clock nets??

can anyone explain me

 

[shelkerahul]

I don’t think any P&R tool fixes the max transition problem, once clock tree is built. Designer has to fix it manually.

 

[vlsitechnology]

so how to fix it manually can anyone tell me?

 

[firewire2035]

adjust your setup.

 

[prithivikumars]

Hi,

Max transition violation is b'caz of more load. To solve that do cloning or insert the high drive strength buffer in that path.

Prithivi.

 

[iwpia50s]

Basically, either you specified a clock slew that is too loose or your cts tool is crap. Try specifying a tighter slew in cts.

 

[vlsitechnology]

How to specify tighter slew in cts ? wt value shd i give their?
in sdc it is given as set_max_transition [current_design] as 1
but i am geting 1.43 which is much larger than 1 so wt shd i do?