Looking for documents on latch up in IC layouts

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Re: Latch up in IC layouts

U have the doc of CMOS latch up...so what are u asking for actually?

In Layout usually, as long as the design rules is followed and the n-well is not floating then I think that we had prevent latch up
 

Re: Latch up in IC layouts

CHECK OUT THIS IGHT DO....
 

Latch up in IC layouts

In usually,the design rules is meeting,the latch up is prevented.
 

Re: Latch up in IC layouts

to avoid latchup in chip,

if the source/drain of transistor is connected to pad make sure that it has it's tap shielded and also ensure that nearby transistors also guarded well
 

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