Looking for documents on latch up in IC layouts

[vijay.kumarreddy]

Latch up in IC layouts

Please find some useful docmunts on the CMOS latch UP in layouts

vijay

 

[Syukri]

Re: Latch up in IC layouts

U have the doc of CMOS latch up...so what are u asking for actually?

In Layout usually, as long as the design rules is followed and the n-well is not floating then I think that we had prevent latch up

 

[vijay.kumarreddy]

Re: Latch up in IC layouts

I've no doubts about latchup.I've kept some useful doc abt latchup.

regards

vijay

 

[YESH_23]

Re: Latch up in IC layouts

CHECK OUT THIS IGHT DO....

 

[alexbsb]

Latch up in IC layouts

In usually,the design rules is meeting,the latch up is prevented.

 

[vdevan77]

Re: Latch up in IC layouts

to avoid latchup in chip,

if the source/drain of transistor is connected to pad make sure that it has it's tap shielded and also ensure that nearby transistors also guarded well