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Layout routing over transistor

Junus2012

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Dear friends,

I usually never routed a metal over active devices, especially transistors, I have this rule from the book Art of analog Layout design.

However, today I was investigating some cells from the foundry, and I have seen they made many cells where they routed over MOS, is that ok ?

Ieven always try to make my vias at the transisor ends, not for example in the middle of the drain/source/gate

Thank you
 

Dominik Przyborowski

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The case is related to harm of polysilicon gate, during etching of (especially) M1 routed over it. So, for matched mosfets coverage should be the same (if not possible to avoid).
The question is what cells has routing over mosfets. For logic cells it is not an issue at all.
 

dick_freebird

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Particularly in technologies with thicker gate
oxides and crappy spacer oxides, the metal
can push field against the channel and the
spacers, summing with the gate field, and
make matching deviate and/or cause
discrepant device drifts (analog often
operates in a bad place for HCE, nearly
the same as your worst case DC hot carrier
reliability test bias of Vds=Vds(max),
Vgs=Vds/2).

For me, I just make sure that anything match-
critical receives identical over-routes; if one
has metal over gate in some fashion, so does
anything meant to match. If that means a stub
that "doesn't need to be there" for routing, so
be it.
 

Junus2012

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Dear friends,

Thank you for your reply

I understand from you that not all the MOS is sensitive to the over routing, only the gate. Also,I conclude from your comment that it is more sensitive to M1, which means if I route with M2 or M3 it will be less problem?


So, for matched mosfets coverage should be the same (if not possible to avoid)
So in case if I routed over one transistor in a matched pair, I must evenly do the same for the other one

The question is what cells has routing over mosfets. For logic cells it is not an issue at all.
The cells I saw was digital cells, however, you reminded me to look for the analog cells, then I will give you feedback


For me, I just make sure that anything match-
critical receives identical over-routes; if one
has metal over gate in some fashion, so does
anything meant to match. If that means a stub
that "doesn't need to be there" for routing, so
be it.
The same question from above, if I route with higher metal level then I will have less problem
 

Dominik Przyborowski

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So in case if I routed over one transistor in a matched pair, I must evenly do the same for the other one
Yep. Look for Hans Tuinhout paper about metal coverage effect on mismatch.

Regarding dick_freebird comment.
Current in the channel is modulated by electric field, so any potential on metal lines can interfering with gate voltage and modify current. Of course as distance of routing to device is higher then effect is smaller (you can imagine it as cap between channel and metal line fighting with gate cap).
Similar mechanism we can observe after irradiation - charged particles generates holes in thick oxide, which induces parasitic channel in nwell, creating drain-source leakage outside transistor. But maybe you don't need to know it yet ;)
 

timof

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"you can imagine it as cap between channel and metal line fighting with gate cap"

Channel is not "seeing" any capacitance to the surrounding routing - because it is fully covered and shielded by the gate.

On routing over active - in the latest technologies, fabs are doing "contact over gate poly" - landing a contact right at the center of the gate poly.
These producst are hitting the stores now (iPhone 12, A14, etc.).
Image sensor folks have been doing this for decades.
 

Junus2012

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Thank you friends,

I have checked the analog cell from my foundry and they didn't route over the gate. but as timof said in the very new technology they are doing it,

I have related question,

In the layout of the MOS transistor, they usually extend the gate a little bit after the active diffusion region, what this indicates? please see the image,

llay.PNG
 

timof

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Poly/gate is always extended outside the diffusion (active, mote, OD, diff) - to provide a better "wrapping" over/around the diffusion (channel), to control the corner (between diffusion and STI) of the channel, and to protect against unavoidable manufacturing variations - like shift between masks for diffusion and poly, so that a part of the channel may become exposed if you sdo not have such extension.

In technologies where contacting poly over active is prohibited, it is this portion of the poly - "field poly" ("POLY NOT ACTIVE" - in SVRF language) - where the gate contact should land on.

Gate contact over active is used not only in the latest FinFET technologies, but also in old technologies where density is of primary importance - e.g., in image sensor designs (CMOS image sensors), that use quite old technologies - 180nm, 130nm, 90nm, etc.
--- Updated ---

The "context" (neighborhood) of the matched devices should be made identical not only from capacitive coupling considerations.
There are also considerations of creating the same environment for the matched devices from the viewpoint of thermal - temperature distribution - so that they "see" the same temperature (metallization may be a significant factor, of how the temperature is distributed over the chip), chemical - as metals above transistors affect diffusion of hydrogen, that passivates defects and may significantly affects Vt, and so on.

And do not forget to check other systematic sources of mismatch, such as parasitics - to make sure that matched devices "see" the same resistances, capacitance, delays, voltage drops, etc.
Ground net may introduce different voltage drops for nominally identical devices - so you should check and protect against that as well, to guarantee a good matching.
 
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Junus2012

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Hello,

I will follow not to rout over the active region, I will use the extended poly gate to put the via, but I came with two possibilities as shown below, in the right one the via is exactly near to the active gate and above the extended part, while in the lift one I put the via near to the extended part

Which one should be more safe ?
llay.PNG
 

timof

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The one on the left may have somewhat lower capacitance (gate to source/drain), the one on the right side has lower gate resistance.
Pick what you like or need.
Make sure your DRC is clean.
 
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