Hi
I have designed my system in Verilog HDL. Can I design Layout in Cadence from verilog code ? If yes then kindly mention steps involved too.
if any related reading material is available then kindly post the links that will be really helpful.
Are you saying that you want to directly generate a design layout from a verilog code? To my knowledge, there is no tool can do that. But if it is not directly, then you just have to follow normal design flow from RTL synthesis, place and route, stream-in into virtuoso to have the design layout.
Are you saying that you want to directly generate a design layout from a verilog code? To my knowledge, there is no tool can do that. But if it is not directly, then you just have to follow normal design flow from RTL synthesis, place and route, stream-in into virtuoso to have the design layout.
hi
friends,
i m harry parker,
i m not know more about this but i thinks this is useful for you.
thank you]
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