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Layout from Verilog code in Cadence

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Eminent.Engineer

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Hi
I have designed my system in Verilog HDL. Can I design Layout in Cadence from verilog code ? If yes then kindly mention steps involved too.
if any related reading material is available then kindly post the links that will be really helpful.

Thanks to all.
 

soloktanjung

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Are you saying that you want to directly generate a design layout from a verilog code? To my knowledge, there is no tool can do that. But if it is not directly, then you just have to follow normal design flow from RTL synthesis, place and route, stream-in into virtuoso to have the design layout.

Thanks.
 

rkvrkpkvtkv

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Are you saying that you want to directly generate a design layout from a verilog code? To my knowledge, there is no tool can do that. But if it is not directly, then you just have to follow normal design flow from RTL synthesis, place and route, stream-in into virtuoso to have the design layout.

Thanks.

hi

1)Synthesis the verilog code using RTL compiler or Design compiler
2)Take the synthesised netlist into the Encounter for Back end design

you can use the text book 'Physical design Essentials' for back end designing

Thanks
 

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