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Problem in Cadence layout

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immajidjafari

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Hello everyone!
I'm trying to design an inverter layout in cadence but when I import a nmos that's the wrong layout with a white box. and Pmos has the correct layout. This is a screenshot from nmos and pmos beside together. tnx


1678307570399.png
 
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dick_freebird

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Might be just an undesirable fill code on one of the NMOS-specific layers. Go look in the LSW for that kind of solid fill and modify to suit?
 

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