digitalo
Newbie level 6
Hi all!
I'm building a standard cell library. Everything is working, but post-P&R digital simulation with SDF backannotation. The most basic IOPATH statements work just fine, but about everything more complex fails.
For example, a DFF with SET input, the SDF contains:
(WIDTH (COND D==1'b0 (posedge SET)) (0.132::0.132))
So in the verilog, I placed
$width (posedge SET &&& D===1'b0, 0:0:0 );
(also tried many similar statements), but I always get
ncelab: *W,SDFNET: Unable to annotate to non-existent timing check (COND (D==0) (WIDTH (posedge SET) (0.132))) of instance Testing.\myreg of module DFFS <testing.sdf, line 1523>.
There must be something fundamentally wrong with my understanding of SDF-to-Verilog mapping. I think that once I get the above statement to work, I will be able to figure out the rest...
So my question is:
What to place in the verilog description to match the SDF entry?
Dirk
I'm building a standard cell library. Everything is working, but post-P&R digital simulation with SDF backannotation. The most basic IOPATH statements work just fine, but about everything more complex fails.
For example, a DFF with SET input, the SDF contains:
(WIDTH (COND D==1'b0 (posedge SET)) (0.132::0.132))
So in the verilog, I placed
$width (posedge SET &&& D===1'b0, 0:0:0 );
(also tried many similar statements), but I always get
ncelab: *W,SDFNET: Unable to annotate to non-existent timing check (COND (D==0) (WIDTH (posedge SET) (0.132))) of instance Testing.\myreg of module DFFS <testing.sdf, line 1523>.
There must be something fundamentally wrong with my understanding of SDF-to-Verilog mapping. I think that once I get the above statement to work, I will be able to figure out the rest...
So my question is:
What to place in the verilog description to match the SDF entry?
Dirk
