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Is there anybody who can help me to optimize this code ?

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hoangthanhtung

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library ieee;
use IEEE.std_logic_1164. all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;

entity count is
port(
load,clk,enb,mode : in std_logic;
data : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0)
);
end count;

architecture behavior of count is

begin
process (load,enb,mode,clk)
variable cnt : integer:=0;
begin
if clk'event and clk='0' then
if enb='0' then
if load='0' then
output <=data;
cnt := conv_integer(data);
else
--------------------
if mode='0' then
if cnt <15 then
cnt := cnt + 1;
else
cnt := 0;
end if;
else
if cnt >0 then
cnt := cnt - 1;
else
cnt := 15;
end if;
end if;
output <= conv_std_logic_vector(cnt,4);
-------------------
end if;
end if;
end if;
end process;
end behavior;

This is up/down counter with control signal clk,enable,load,up/down direction. I also synthesize it successfully by using Synopsys VHDL compiler but I think it does optimize. Is there anybody can help me ?

Thank in advanced
 

arunragavan

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Well i have done compiler level optimization.. under standard ASIC..library.. the SCL05u library..

i have attached the files.. jes download and take a look at it..
 

hoangthanhtung

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arunragavan said:
Well i have done compiler level optimization.. under standard ASIC..library.. the SCL05u library..

i have attached the files.. jes download and take a look at it..

I wonder about SCL05u library. It is free or commercial libarary. If it is free, could you send it to me by me email httung@asic.korea.ac.kr.

I use Samsung std90 (0.35 um technology), so I want to change to use other library to compare.

Thank you for replying.
 

nemolee

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Do not use comparator in your design for example > or <.
You just need to use (X == 4'hF) in your design.
 

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