hoangthanhtung
Full Member level 3
library ieee;
use IEEE.std_logic_1164. all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity count is
port(
load,clk,enb,mode : in std_logic;
data : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0)
);
end count;
architecture behavior of count is
begin
process (load,enb,mode,clk)
variable cnt : integer:=0;
begin
if clk'event and clk='0' then
if enb='0' then
if load='0' then
output <=data;
cnt := conv_integer(data);
else
--------------------
if mode='0' then
if cnt <15 then
cnt := cnt + 1;
else
cnt := 0;
end if;
else
if cnt >0 then
cnt := cnt - 1;
else
cnt := 15;
end if;
end if;
output <= conv_std_logic_vector(cnt,4);
-------------------
end if;
end if;
end if;
end process;
end behavior;
This is up/down counter with control signal clk,enable,load,up/down direction. I also synthesize it successfully by using Synopsys VHDL compiler but I think it does optimize. Is there anybody can help me ?
Thank in advanced
use IEEE.std_logic_1164. all;
use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;
entity count is
port(
load,clk,enb,mode : in std_logic;
data : in std_logic_vector(3 downto 0);
output : out std_logic_vector(3 downto 0)
);
end count;
architecture behavior of count is
begin
process (load,enb,mode,clk)
variable cnt : integer:=0;
begin
if clk'event and clk='0' then
if enb='0' then
if load='0' then
output <=data;
cnt := conv_integer(data);
else
--------------------
if mode='0' then
if cnt <15 then
cnt := cnt + 1;
else
cnt := 0;
end if;
else
if cnt >0 then
cnt := cnt - 1;
else
cnt := 15;
end if;
end if;
output <= conv_std_logic_vector(cnt,4);
-------------------
end if;
end if;
end if;
end process;
end behavior;
This is up/down counter with control signal clk,enable,load,up/down direction. I also synthesize it successfully by using Synopsys VHDL compiler but I think it does optimize. Is there anybody can help me ?
Thank in advanced