Is possible for hold time to be 0ns??

[ilikebbs]

If possible, how to do for it?

 

[mm_zhou1983]

why not
with the crosstalk with other wires it can be 0 or negative

 

[tronix]

It is infact zero for Master Slave Configuration

 

[ilikebbs]

Hi,all
Please read the question carefully.I do not think your reply is relevant with my question.

 

[FPGAs]

I think all flip-flop are made of real analog circuits.
The hold time can be nearest to 0ns if analog circuit are good enough

 

[salma ali bakr]

it can be near 0ns...very small indeed
but never ZERO for real

 

[zlop]

I agree with
salma ali bakr.

 

[bpu]

real hold time always more than 0 ns. but the clock tree can have short delays (with comparison to data paths), than more or equal than hold time of real flip-flop elements of fpga. if this delay is equal to real hold time, that we have 0 ns hold time in fpga. if more, than we can have negative hold time.
this delays are defined by engineers, who design fpga core.

 

[salma ali bakr]

hi bpu,

can u clear ur point more please
i'm interested to understand what u mean

thanks,
Salma

 

[tkbits]

View this image.

Interval (t2,t4) must satisfy the setup time of the FF, and (t4,t5) must satisfy the hold time of the FF. Assume the hold time (t4,t5) is always positive for the FF.

The time intervals (t1,t2) and (t3,t5) represent propagation delays through the input buffer. Because of the delay, t3 can precede t4.

If the interval (t4,t5) satisfies the FF hold time requirement and t3 precedes t4, then the whole circuit has a negative hold time requirement for DIN with respect to CLK.

 

[omara007]

from the FF prospective, there should be a hold time and it's irrelevant of the design u r doing .. u can find it in the library documentation.

for the hold time from the circuit point of view, it will be relative to the clock as u guys have said.