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is 7.5mm*7.5mm a big chip for 0.35um CMOS technology?

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wateror

wateror

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I am designing a IC which may need 7.5mm*7.5mm area. Is there any possible issue in such a big chip? thanks
 

well there might be lot of process dependendent issues. WHich proces your are working on??
 

There will be a lot of issues if you are a new designer, but incase you know some of the basic issues which again are process dependent then there will not be a big issue. But the size is chip is big enough so you have to take care of the coupling between the interconnects and the possible delay caused by them :D. Also it depend upon the density of your design.
 

depends what you're designing... for a transceiver thats okay... for an inverter you're going a bit overboard...
 

yeah, thanks,everyone
 

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