Invoking different always constructs at different signals

[naizath12]

Within the same module, I am not able to invoke different always constructs at posedge of different signals.

Eg.,

Module( )

Wire out;
Assign out = signal_in && clk;

Always @( poseDge clk) .......;

Always @( posedge out) .......;

endmodule

When I check the rTd schematic, the D modules inside are all clocked by the clk and not as I expected ie., 1st D by clk and 2nd D by out

Help

 

[shitansh]

Re: Invoking different always constructs at different signal

Hi,

Normally it is recomanded to not used gated clock signal, since with gated clock there is clock skew problem and it is little bit tricky to handle clock skew, instead you can use below shown method.

Here in your case you are using out which is gated clock, if you want to use posedge of out then try to use this way

always @ (posedge clk)
begin
if (out) // means posedge of (clk & out)
test <= (/*input data*/);
else
test <= test;
end

HTH
--
Shitansh Vaghela

 

[naizath12]

Re: Invoking different always constructs at different signal

Thnx....will try n come bck to u

 

[shitansh]

how to use gated clock

Hi,

You can also try this way.........., Also make sure that signal_in is not tied to 1'b0 always.

Module( )

// wire out;
// Assign out = signal_in && clk;

reg out = 1'b0;
wire clock = clk ;

always @ ( posedge clk or negedge clock )
begin
if (signal_in)
out <= (~out);
end

Always @( posedge clk) .......;

Always @( posedge out) .......;

endmodule


HTH
--
Shitansh Vaghela