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[SOLVED] Adding std_logic signals with unsigned signals

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dpaul

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The tx_data_length needs to be calc which is a signal of type unsigned. The parity_en_i and stop_bit_count_i are of types std_logic and can only be '0' or '1' (these two single bit inputs are outputs from a register in another module).
Unsigned addition needs to be performed for the tx_data_length. I am trying to maintain that the LHS and RHS signals must all of type unsigned.

Is this the best way to perform such an operation?

Code:
.
.
-- Ports declarations
        parity_en_i             : in    std_logic;
        .
        .
        stop_bit_count_i        : in    std_logic;
        .
        .
architecture arc of module_arch is

-- Signal declarations
.
.
signal tx_data_length : unsigned(3 downto 0);
signal data_length      : unsigned(3 downto 0);
.
.
signal parity_en      : integer range 0 to 1;
signal stop_bit_count : integer range 0 to 1;

begin

    parity_en <= 1 when parity_en_i = '1' else 0;
    stop_bit_count <= 1 when stop_bit_count_i = '1' else 0;
.
.
.
    tx_data_length <= 1 + data_length + to_unsigned(parity_en, 1) + 1 + to_unsigned(stop_bit_count, 1);
.
.

Update: More suitable header - Adding data-types std_logic and unsigned in VHDL
 
Last edited:

1) Why on earth is parity_en an integer and not a std_logic?
2) Same for stop_bit_count.
3) if you use ieee.numeric_std library and change those integers to std_logic then I don't think you need the to_unsigned function (not sure about that one.)
 

1. It was std_logic when then value is fed in to the design using a port. Next it is converted to an integer (integer to unsigned is achieved easily) because it needs to be used in an equation where the LHS is unsigned.
2. Same logic as above

If you disagree with my conversion process, do you agree with the one below? Or do you have a better one?
tx_data_length <= 1 + data_length + parity_en_i + 1 + stop_bit_count_i;

Note that parity_en_i and stop_bit_count_i are of type std_loigc and can be either '1'/'0'.
Possibly the compiler (Modelsim) will flag an error for the above statement -- not sure!

But my VHDL brain compiler makes my stop in writing such statements in which dissimilar types are used for an unsigned arithmetic operation.
 

Code:
signal tx_data_length : unsigned(3 downto 0);
signal data_length      : unsigned(3 downto 0);

signal parity_en      : unsigned(0 downto 0);
signal stop_bit_count : unsigned(0 downto 0);

begin

    parity_en(0) <= parity_en_i;
    stop_bit_count(0) <= stop_bit_count_i;
.
.
.
    tx_data_length <= 1 + data_length + parity_en + 1 + stop_bit_count;
 
Code:
function sl2i(sl: std_logic) return integer is
begin
    if sl = '1' then 
        return 1; 
    else 
        return 0;
    end if;
end;
begin
    tx_data_length <= 1 + data_length + sl2i(parity_en_i) + 1 + sl2i(stop_bit_count_i);
 
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