#### rafimiet

##### Member level 5

I am trying to make a generic design for a filter. The filter works on different sizes of inputs from 2x2 to 64x64 and therefore the input needs to be multiplied by a coefficient matrix of corresponding sizes. I tried the following:

c_mult chooses between constants of different sizes.

Then I tried the following:

But again, it is not simulatable and I get the following error:

Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 subtype t_dim1 is signed; type t_dim1_vector is array (natural range <>) of t_dim1; type t_dim2_vector is array (natural range <>) of t_dim1_vector; constant c_mult : t_rom_vector2 := c_dct2_b2 when (g_bl_size = 2 and g_tr_type = 0) else c_dct2_b4 when (g_bl_size = 4 and g_tr_type = 0) else c_dct2_b8 when (g_bl_size = 8 and g_tr_type = 0) else c_dct2_b16 when (g_bl_size = 16 and g_tr_type = 0) else c_dct2_b32 when (g_bl_size = 32 and g_tr_type = 0) else c_dct2_b64 when (g_bl_size = 64 and g_tr_type = 0) else c_dct8_b4 when (g_bl_size = 4 and g_tr_type = 1) else c_dct8_b8 when (g_bl_size = 8 and g_tr_type = 1) else c_dct8_b16 when (g_bl_size = 16 and g_tr_type = 1) else c_dct8_b32 when (g_bl_size = 32 and g_tr_type = 1) else c_dst7_b4 when (g_bl_size = 4 and g_tr_type = 2) else c_dst7_b8 when (g_bl_size = 8 and g_tr_type = 2) else c_dst7_b16 when (g_bl_size = 16 and g_tr_type = 2) else c_dst7_b32 when (g_bl_size = 32 and g_tr_type = 2);

c_mult chooses between constants of different sizes.

**I synthesized this but it seems that it is not simulatable...**Then I tried the following:

Code VHDL - [expand] 1 2 3 4 5 type t_rom_vector3 is array (natural range <>) of t_rom_vector2; constant c_trtype_blsz : t_rom_vector3 := ( (c_dct2_b2, c_dct2_b4, c_dct2_b8, c_dct2_b16, c_dct2_b32, c_dct2_b64), (c_zero, c_dct8_b4, c_dct8_b8, c_dct8_b16, c_dct8_b32, c_zero), (c_zero, c_dst7_b4, c_dst7_b8, c_dst7_b16, c_dst7_b32, c_zero) );

But again, it is not simulatable and I get the following error:

(82) At depth 2, array length is 6; aggregate length is 126

(83) At depth 2, array length is 6; aggregate length is 64

(84) At depth 2, array length is 6; aggregate length is 64

**So is there a way of generating a generic code for this?***<Moderator action: changed to syntax vhdl tag for VHDL syntax highlighting>*
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