vcnvcc
Full Member level 2
Hello,
This question is asked to one of the Engineer at principle level in interview.
Question is Suppose you have a design in a chip with 350nm technology, now same design if we migrate to 130nm, what challenges and issues you face?
Now I am placing my self at that position and trying to answer that question
Lets say, I have divided those issues and challenges in to
- RTL Design and integration
- Verification
- Synthesis
- STA
- PNR
1. I say RTL – Design & verification will have no effect, it is technology independent.
2. Synthesis & STA – since technology is smaller, we’ll face issue in timings. (May be more- I don’t know)
3. PNR – I don’t know. :-(
In first place I know that we are refereeing to channel length in name of process, but I don’t understand whats change in device/transistor, characteristic/voltage etc..
Please share your info/knowledge, I’ll be glad to say to Thanks.
Thanks with smile.
This question is asked to one of the Engineer at principle level in interview.
Question is Suppose you have a design in a chip with 350nm technology, now same design if we migrate to 130nm, what challenges and issues you face?
Now I am placing my self at that position and trying to answer that question
Lets say, I have divided those issues and challenges in to
- RTL Design and integration
- Verification
- Synthesis
- STA
- PNR
1. I say RTL – Design & verification will have no effect, it is technology independent.
2. Synthesis & STA – since technology is smaller, we’ll face issue in timings. (May be more- I don’t know)
3. PNR – I don’t know. :-(
In first place I know that we are refereeing to channel length in name of process, but I don’t understand whats change in device/transistor, characteristic/voltage etc..
Please share your info/knowledge, I’ll be glad to say to Thanks.
Thanks with smile.