Interview question - Migrating to smaller technology.

[vcnvcc]

Hello,

This question is asked to one of the Engineer at principle level in interview.

Question is Suppose you have a design in a chip with 350nm technology, now same design if we migrate to 130nm, what challenges and issues you face?

Now I am placing my self at that position and trying to answer that question
Lets say, I have divided those issues and challenges in to
- RTL Design and integration
- Verification
- Synthesis
- STA
- PNR

1. I say RTL – Design & verification will have no effect, it is technology independent.
2. Synthesis & STA – since technology is smaller, we’ll face issue in timings. (May be more- I don’t know)
3. PNR – I don’t know. :-(

In first place I know that we are refereeing to channel length in name of process, but I don’t understand whats change in device/transistor, characteristic/voltage etc..

Please share your info/knowledge, I’ll be glad to say to Thanks.
Thanks with smile.

 

[morris_mano]

Some of the issues and challenges in lower nodes are leakage current increases so static power loss increases, interconnect delay becomes significant compare to gate delay so prelayout and post layout timing difference increases, mask for the die becomes more complex so number of layout design rules increases.

 

[vcnvcc]

Thanks morris_mano.

So here again one more question pops up - The size if single device/transistor/cell will be smaller in lower nodes? OR it is same as that of higher 'um' technology?


What about its operating voltage? is there any change in in voltage (I means it is less?)

 

[soloktanjung]

single device/transistor/cell will be smaller in lower nodes?

Yes.

is there any change in in voltage (I means it is less?)

Yes.

 

[abhiverma812]

Hey,

This is basically a problem of scaling down. As we scale down in technology (say by factor of S), most of the parameters will change. New voltage will be V/S, Current will be I/S. Power will reduce by 2 times (P/S^2), Oxide capacitance as Cox.S, length by L/S and Width as W/S .
Apart from this, as the channel length is decreased further (say for technology nodes less then 90 nm) there may be some short channel effects. These includes higher sub-threshold leakage current, Drain induced barrier lowering, hot carrier injection into oxide etc.

Best Regards,
Abhishek

 

[vcnvcc]

Thank you!!

One question over here, I though in some different way and searched it over internet.

Eventually going to lower nodes only to make size of transistor small, rest other parameters like voltage etc I want to make it same, Is this valid???

Why I am asking this because -think that already you have chip - working chip with some "X" technology, now if you port that chip to smaller technology, and if you voltage reduces (lets say 5 v to 1 v) in that case that same chip with smaller technology will not work?
Is my question is valid??

Please put some light & share your insights, if you know. Thanks

 

[abhiverma812]

Hey,

I guess when you are talking about technology scaling down, you are talking about pre-chip fabrication. I am not too sure if we can use a chip with older technology with new scaled down technology. However, I think there must be some mechanism in which you can provide backward compatibility.

Abhishek

Thank you!!

One question over here, I though in some different way and searched it over internet.

Eventually going to lower nodes only to make size of transistor small, rest other parameters like voltage etc I want to make it same, Is this valid???

Why I am asking this because -think that already you have chip - working chip with some "X" technology, now if you port that chip to smaller technology, and if you voltage reduces (lets say 5 v to 1 v) in that case that same chip with smaller technology will not work?
Is my question is valid??

Please put some light & share your insights, if you know. Thanks

 

[vcnvcc]

Abhishek,
So what you are saying we can not use latest technology to those chips which are in market and which used older technology?

Members, can you please share your comments, even I am not sure for that.

Thanks.

 

[englishdogg]

hmm .. this is interesting and i am sure that you can perform technology re-mapping.. if I have understood correctly you wish a 90nm design now to be mapped at say for eg 45nm.. if yes then this is doable.

But accordingly your SDC and other constraints should also be modified for reasons that are mentioned above witnessed while migrating to shrinking technologies.

A flow per say would be from DC usage perspective
- In library setup use 90nm as link libraries and 45nm as target libraries
- Perform incremental compile

From RC perspective
- Load both libraries together 90 / 45nm to the library attribute
- Set an avoid / set_dont_use true on the 90nm libraries
- Perform an incremental optimization

Let me know if this works

 

[micpro]

Hello,

Lets say, I have divided those issues and challenges in to
- RTL Design and integration
- Verification
- Synthesis
- STA
- PNR

You seem to think only about digital design. But if you migrate from 350nm to 130nm in 2012, I guess you don't care about high digital performance, but the design rather includes a lot of analog blocks? Flash? RF? MEMS? Migrating these parts will give you a lot more headache than the digital part ...

 

[englishdogg]

I did not mean to ignore.. was just answering the question to the point.
Now when you migrate to a lower technology your hard macros or hardened macros also need to be migrated to lower technologies. So does the analog macros need to change or replace it with a corresponding available block for that technology with the same function.

Can you elaborate when you say headache? what exactly the problem are you refering to.. obviously there is an effort involved in performing simulations etc but if the design spec calls for it then its just an effort.

 

[saurabhr8here]

I will try to answer this question in two parts.

For older technology nodes (>65nm):
Transferring a design from one technology node to another would be comparitively easier, because directly scaled versions of your designs would work with slightl tweaking. You'd have to apply a scaling factor (~0.7X) to all your layouts and metal pitches. The transistor length scales directly, however, width tuning might be required to optimal timing etc. Basically, you can have a new standard cell library that is scaled and go ahead with synthesis-P&R. I do not have detailed knowledge beyond extraction, hence cannot comment what else would be required at SP&R while transferring to a new node. As someone mentioned earlier, wire RC goes higher at scaled nodes, so you might end up with a different distribution between wire and gate delay.

For post 65nm technologies, especially at 28/20/14nm nodes:
There is absolutely no way to use the exact same layouts and scale them. This is because, lithography has become extremely complicated and a lot of foundries utilize double-patterning methods to print the layers. Hence, every new node has very specific design rules and getting a DRC clean design can be tedious. Additionally, leakage power increases with technology scaling and since most recent designs are power limited, careful consideration to leakage/standby power is required when moving to newer technologies.

Wire, local interconnect and contact R/C increases considerably at sub-32nm nodes. Hence, post extracted analysis and re-optimization migh be necessary. Local variation increases with newer technology and a better understanding of the distribution of global to local variation is important at newer technology nodes. Temperature behavior of transistors with scaled nodes is different. Depending on supply voltage scaling and the Vt flavor of transistors used its possible that low temperature is the slow corner instead of the traditional high temperature corner. Strain technology, especially in PMOS transistors increases its drive strength considerably, so P/N drive strength is improving with scaling, hence all gates need to be resized to take into account this effect.

There are many more modifications required when scaling to a new technology node and simple re-mapping is not feasible for newer generations.

 

[mail4idle2]

Is there any book explaining all the points we discussed above ?
Thanks