I will try to answer this question in two parts.
For older technology nodes (>65nm):
Transferring a design from one technology node to another would be comparitively easier, because directly scaled versions of your designs would work with slightl tweaking. You'd have to apply a scaling factor (~0.7X) to all your layouts and metal pitches. The transistor length scales directly, however, width tuning might be required to optimal timing etc. Basically, you can have a new standard cell library that is scaled and go ahead with synthesis-P&R. I do not have detailed knowledge beyond extraction, hence cannot comment what else would be required at SP&R while transferring to a new node. As someone mentioned earlier, wire RC goes higher at scaled nodes, so you might end up with a different distribution between wire and gate delay.
For post 65nm technologies, especially at 28/20/14nm nodes:
There is absolutely no way to use the exact same layouts and scale them. This is because, lithography has become extremely complicated and a lot of foundries utilize double-patterning methods to print the layers. Hence, every new node has very specific design rules and getting a DRC clean design can be tedious. Additionally, leakage power increases with technology scaling and since most recent designs are power limited, careful consideration to leakage/standby power is required when moving to newer technologies.
Wire, local interconnect and contact R/C increases considerably at sub-32nm nodes. Hence, post extracted analysis and re-optimization migh be necessary. Local variation increases with newer technology and a better understanding of the distribution of global to local variation is important at newer technology nodes. Temperature behavior of transistors with scaled nodes is different. Depending on supply voltage scaling and the Vt flavor of transistors used its possible that low temperature is the slow corner instead of the traditional high temperature corner. Strain technology, especially in PMOS transistors increases its drive strength considerably, so P/N drive strength is improving with scaling, hence all gates need to be resized to take into account this effect.
There are many more modifications required when scaling to a new technology node and simple re-mapping is not feasible for newer generations.