Internal 3-state replace multiplexer?

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davyzhu

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I have read a techxclusive from Xilinx named "Timing closure", it suggest that we should 'Use internal three-state buffers to replace large multiplexers', because 'Virtex based FPGAs use dedicated AND-OR logic to implement three-state buffers', and 'Can reduce multiplexer delays'.

I was told that internal 3-state should be avoid when design asic, but why the xilinx suggestion? Anyone have the experience? And I am curious to know how to implement 3-state in AND-OR logic?

DAVY
 

In asic design, you should use mux instead of tri,

because tri will increase power consumption and

increase DFT's difficulty.




 

Hi,
Yes long back I have done this in my design targeted to FPGA.
I replaced all muxes in my design by tristate muxes. This was needed
because FPGA have limited routing resources and tristate buffer delay
is much less compare to mux formed using F and G function generators.
In ASIC also some times to avoid routing conjestion (particularly in
case of huge no. of configuration registers ) one can use internal tri state
bus. This will make life somewhat complicated from DFT point of view
but its OK!
 

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