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tri-state buffer in sram array

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parminder

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what is the use of tri-state buffer in sram array. suppose only 1 bit data has to be read and write in the sram. will there be still requirement of these buffers.

image for reference.
 

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The data lines may be bidirectional (typically so in SRAM) and the
wraparound from the output data to input data has to be broken
to get a clean read, rather than forcing the last read's data back
onto the core data lines. Tristate lets the selected cell(s) push the
data bus lines (which are also the sense amp inputs).
 

if i am designing circuit like this , is there anything missing in the circuit (here suppose , i have taken 1 bit Din ).
 

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