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Why do some DMACs with two synchronous and dedicated (not shared with CPU) AHB MASTER interfaces uses internal FIFOs? E.g.: ARM's PL080 has a 4-word internal FIFO... what's the big advantage of that?
The FIFO is meant for data.You would want to look at the part/board to see if the FIFO is for data or DMAC setup.
WRT data, the DMAC is reading from one interface and writing to the other. If the writing interface stalls, the read can complete a couple of operations before it stalls. They must be confident the busses are well balanced as I would expect the FIFO to be larger.
WRT DMAC setup, you could be queueing up the next operation in a FIFO as well.