interconenct model in pre-layout timing

[tangqin55]

When using RTL compiler.
I used the following setups:

set_attribute wireload_mode top
set_attribute interconnect_mode ple
set_attribute library {nldm.lib}
set_attribute lef_library {**.lef}
set_attribute cap_table_file {**.capTbl}
........
synthesize -to_generic -effort high
synthesize -to_mapped -effort high -csa_effort high
synthesize -to_place


In many case, the resistance contribution in the wireload models is set to 0 in this pre-layout timing analysis.
However, in the .lib file, the resistance of any wire_load is given. such as:
wire_load("1K_hvratio_1_4") {
capacitance : 1.774000e-04;
resistance : 3.571429e-03;
area : 7.559700e-02;
slope : 5.000000;
fanout_length( 1, 1.3207 );
......
}
Furthermore, since I add the lef file and capTbl file, the resistance and capacitance of each segment of wire should be available.

If the complier doesn't use the resistance information for timing check, what's the meaning to add .lef and .capTbl file? We even don't need to define the unit-length-resistance in .lib file.

Does complier calculate delay and slew considering the resistance of wires?
If yes, how to get those values?

 

[tangqin55]

:?::?::?:
anyone can help me?