Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

integrated bipolar transistor

Status
Not open for further replies.

brunokasimin

Member level 4
Joined
Jun 13, 2008
Messages
70
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,828
can somebody explain me about lateral pnp- transistor and pnp-substrate transistor?

what are their diefferences?
 

alan hasting's book discussed it. if you don't have the book i'll try to discuss it.
 

Vertical is just like a vertical NPN. This requires extra (costly and yield degrading) diffusions.

Lateral is where there is a top N layer and two P diffusions take place very close together laterally. The base width is large and the base doping is not optimum. You rarely get anything more than a few MHz of gm/c
 

The difference relies on the way you fabricate them.

Take a look at the pictures... if you don't get them, just let me know and I'll explain.

diemilio
 

in a substrate PNP transistor, the substrate acts as the collector it's operation is vertical just what the other posters said.
 

forkschgrad said:
in a substrate PNP transistor, the substrate acts as the collector it's operation is vertical just what the other posters said.

forkschgrad is completely right!! In the substrate BJT you don't have access to the collector cause this will be your substrate. This means that it will always be tied to the lowest voltage in your circuit!!

diemilio
 

In a normal CMOS process, you have two types of "free" bipolars ( both pnp ):

1. Verical pnp: This is formed by (emitter: p+ diffusion on an NWELL, base: n+ diffusion on the same NWELL, collector: p+ diffusion on the substrate ( that lies below the NWELL ). This is the most commonly used bipolar in CMOS bias cells.

2. Lateral PNP: same as above except that the collector is made by p+ diffusion on NWELL. This makes the structure very similar to a PMOS transistor. You have two problems in this BJT:
1st: a "parasitic PMOS" may turn on. This is solved by adding a gate between emitter and collector diffusion and applying a +ve potential to it (effectivelly closing the parasitic PMOS)

2nd: a parasiic pnp which is the very same vertical PNP above. With a lateral PNP you will, inevitably, have another parasitic vertical pnp in parallel. This makes a fraction of the collector current go to substrate
 

Also lateral pnp have r(miu) (collector-base resistance) almost beta-ro(smaller than at the other) which means it must be taken in account at the output resistance formulas.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top