Integrated PGA design problems for 24-bit delta sigma modulator

[RingFinal]

A PGA is required for a high precision DSM ADC, with function of providing 1~128 signal gain, rail-to-rail input/output, buffering the ADC's SC sampling circuits. Other requirements are also critical: high input impendace, low noise/aliasing, low offset, low power, low INL.

There are generally 2 kinds of strcuture:
1) Resitive Feedback using two OPAs, Buffers are required to driving S/H stage.
2) Capacitive coupled PGA using 1 OPA, input precharge buffers are required to provide high input impendance.

Main challenges:
1) Driving capacibility is conflict with low alasing, Anti-Aliasing Filter is requried before S/H stage, but this will degrade the settling.
2) varieties of dynamic techniques are used to improve settling without bringing noise problem. e.g. precharge, dynamic filter. BUT the switch's glitch become another serious problem.
3) Even I have solved all probems listed below, the power consumption is relatively high compared with industry benchmark.

I read many IA's papers (Huijsing, e.t.), but these IAs are usually designed for monolithic chip, usually a very large decoupling cap is conencted at the output.

Could anyone help point out any mistake of my understanding above? or provide any inspiration, materials about integrated PGA? Thank you very much!

 

[KlausST]

Hi,

A proper design starts with numbers: You should decide the target specifications.
Currently we see just two numbers:
* 24 bits resolution
* 1..128 gain of PGA

What is
* the signal frequency of interest (signal bandwidth)?
* expected sampling frequency?
* expected data rate?
* input signal voltage range?
* max allowed distortion of the analog signal?
* accuracy of the input signal?
* precision of the input signal?

What is the goal of the application?

Don't
To me as an experienced measurement electronics designer ... I often see requirements in this forum where the members did not do the simplest calculations.
In my job I did a lot of ADC projects, but I'm rather sure I've never seen an ADC with 20 bits precision or better. In other words the 4 LSBs of a 24 bit ADC are useless.
I guess my "best" designs had about 18 bits accuracy (@ some kHz of signal frequency).

I'm doing simple math for you:
--> 24 bit resolution @ 3.3V input voltage range equals to about 200nV
--> with a gain of 128, the resolution goes down to 1.5nV

In my whole carrier I can not remember that I've heard about an Opamp with 200nV output performance, neither DC nor in the some kHz bandwidth.
.. and surely there is no way to get 1.5nV performance.

So let's stay at the 200nV performance. (3.3V, gain of 1)
Any resistor causes noise. Higher value, higher noise.
A resistor in the range of 70 Ohms is expected to cause about 200nVpp noise (@ 1kHz BW).
(The true noise value depends on material, production method, size...)
This means: just imagine you have a perfect zero noise input signal (impossible) and you have a perfect no noise, no offset, no distortion Opamp (also impossible) then a feedback resistor of 70 Ohms or more destroys the 24 bit performance.

Very good Opamps maybe have an input noise performance of 50...100nVpp. With a gain of 128 this means at least 10,000nVpp output noise.

In the end, what does this mean:
Even if you have an extrememly low noise, low voltage source, adding an Opamp may rather reduce than improve overall performance.

But: it all depends on the requirements of your application and your skills ... and still there are physical limits you can't ignore.
If you want best performance ... it's a lot of engineering work to do before even think about using an Opamp.
For one application I've spent months to do math, simulations, Opamp selection, other parts selection (resistor values, resistor types, analog switches, cables, wiring methods, shielding, power supply, reference voltage ....) to get almost best performance, but still far from being 24 bits.

And yes: there are many 24 bit systems around. But most of them don't even have 16 bit performance. The rest is just a marketing number.

Klaus

 

[RingFinal]

Hi,

A proper design starts with numbers: You should decide the target specifications.
Currently we see just two numbers:
* 24 bits resolution
* 1..128 gain of PGA

What is
* the signal frequency of interest (signal bandwidth)?
* expected sampling frequency?
* expected data rate?
* input signal voltage range?
* max allowed distortion of the analog signal?
* accuracy of the input signal?
* precision of the input signal?

What is the goal of the application?

Don't
To me as an experienced measurement electronics designer ... I often see requirements in this forum where the members did not do the simplest calculations.
In my job I did a lot of ADC projects, but I'm rather sure I've never seen an ADC with 20 bits precision or better. In other words the 4 LSBs of a 24 bit ADC are useless.
I guess my "best" designs had about 18 bits accuracy (@ some kHz of signal frequency).

I'm doing simple math for you:
--> 24 bit resolution @ 3.3V input voltage range equals to about 200nV
--> with a gain of 128, the resolution goes down to 1.5nV

In my whole carrier I can not remember that I've heard about an Opamp with 200nV output performance, neither DC nor in the some kHz bandwidth.
.. and surely there is no way to get 1.5nV performance.

So let's stay at the 200nV performance. (3.3V, gain of 1)
Any resistor causes noise. Higher value, higher noise.
A resistor in the range of 70 Ohms is expected to cause about 200nVpp noise (@ 1kHz BW).
(The true noise value depends on material, production method, size...)
This means: just imagine you have a perfect zero noise input signal (impossible) and you have a perfect no noise, no offset, no distortion Opamp (also impossible) then a feedback resistor of 70 Ohms or more destroys the 24 bit performance.

Very good Opamps maybe have an input noise performance of 50...100nVpp. With a gain of 128 this means at least 10,000nVpp output noise.

In the end, what does this mean:
Even if you have an extrememly low noise, low voltage source, adding an Opamp may rather reduce than improve overall performance.

But: it all depends on the requirements of your application and your skills ... and still there are physical limits you can't ignore.
If you want best performance ... it's a lot of engineering work to do before even think about using an Opamp.
For one application I've spent months to do math, simulations, Opamp selection, other parts selection (resistor values, resistor types, analog switches, cables, wiring methods, shielding, power supply, reference voltage ....) to get almost best performance, but still far from being 24 bits.

And yes: there are many 24 bit systems around. But most of them don't even have 16 bit performance. The rest is just a marketing number.

Klaus

Thank you Klaus, you are right, I do need to re-examine the system specifications.
- The design is for precision DC signal measurement.
- DSM Fs=256KHz, ODR=2.5 SPS, PGA Gain=128, ENOB(p2p)=19.1
- PGA typical Spec. input current 1nA, offset 2uV, INL=3ppm, 19nVRMS @2.5 SPS
**
So, I need to design prbably a PGA with input noise of 20nV/sqrt(Hz) with consideration of sampling aliasing.
- Deisgn Res-Feedback IA using 2 OPAs, divide 128 into two gain stages, then I need 4 OPAs. To achive required settling, 2 more buffer needed, now I need 6 OPAs.
- I konw the pre-gain stage could suppress the post-stage's noise, but I still need to carefully balance the buffer's bandwidth and sampled noise.
- After ping-pong/az/choping, the residual offset mainly caused by input chopper switch, the input impedance is also related to this switch. I need bootstrap switch, and even a DAC to compensate the parasitic cap mismatch.
**
OK, everything is fine, how much current do you think I need to achive this PGA. 500uA is very hard for me, while one TI's product consume 250uA including ADC!!?? Not in duty-cycle mode !!??
Besides. the PGA's power consumption is different under different gain, I know this is easy for capacitive coupled IA. But for resistive IA with 2 OPA, at low gain, except of bypass one gain stage, what else method could I to decrease the power consumption? I know the noise performance is looser at low gain configuration. so I could decrease both gm and cc (because of common mode feedback stability) to reduce power? is this right?
**
Your reply is a great help to me. I would be very grateful if you could further point out any mistakes above!

 

[KlausST]

Hi,

Good informations.
But I´m a bit confused now. Is this "IC design"?
If so, then the thread should be moved to the IC design section ... and sadly I have no experience with IC design.

Otherwise: could you give some part numbers?

Please clarify.

Klaus

 

[RingFinal]

Hi,

Good informations.
But I´m a bit confused now. Is this "IC design"?
If so, then the thread should be moved to the IC design section ... and sadly I have no experience with IC design.

Otherwise: could you give some part numbers?

Please clarify.

Klaus

Yes.. It's IC design, could you help move this to "IC section"?
the SPECs are mainly form ADS124S08

 

[FvM]

Done