# IIR implementation in a CPLD

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#### vaf20

##### Full Member level 3 hi all my friend
i would like to implement following simple one order IIR filter in a xc95108 .
H(z) = Y/X = K*(aZ+1)/(bZ+1)
where X are 8 bit's as input and Y as output.also,K,a and b are input's with 8 bits width .
could anyone tell me which -new-algorithm can i use to success to implement ?
any idea!
tnx Hi,
Maybe I am wrong, but it looks like

just clock the signal:
Y <= K * a /b;
but this one looks more like H(z+1) = K*(aZ/bZ) to me!

BR,

#### vaf20

##### Full Member level 3 in the case of H(z) i mean a typical transform function.suppose a simple and first order IIR filter with a zero at 1/a and a pole at 1/b .
all a right?
tnx

#### nand_gates Hi,

Conver ur transfer function to difference equation
H(z) = Y/X = K*(aZ+1)/(bZ+1)

--> Difference eq.
y[n] = (1/b) *{ K*a*x[n] + x[n-1] - y[n-1]};

You can implement this one in Verilog.

#### vaf20

##### Full Member level 3 as u know there is no multiplier in CPLD and include pure logic.
the difference equation u mentioned have same multiplier -and i think same logic-in contrast to my transfer function.am i right? so i think i can not save area ! ok?
any help ...
tnx my friend

#### nand_gates Hi,
Yes its same as ur tranfer function. One more thing to be noted here..
you can design ur coefficeint to be multiplied less than 1. Viz 0.5 =1/2,
0.25 = 1/4 0.625=1/8 .....
so that instead of multiplier you can use shift operation.

You can refer to following book...
Digital Signal Processing with Field Programmable Gate Arrays
by U. Meyer-Baese

Its available here in this forum!

-nand_gates HI Vaf,
The 95108 does not have enought macrocells and most importantly product terms to deal with this problem.

You can solve it by changing your algorithem into a pipelined code, and use an external memory to store your constants, create a state machine that does your calculation with only one multiplier and one adder.

You maybe able to do it without the memory, but it needs a lot of thinking before hand.

First, create a block to multiply 2 8 bit values. And one to do the addition.

Create a state machine to have enough steps to do your calculation one step at a time using the adder and multiplier blocks.

For example if you want to do a a*b - c*d + e

You make 5 states for the calculation, the minus, can be handled by negate the result of the operation.

I am still not convinced this can be done inside a 95108 but it will be a good practice to fix it, it is an interesting challenge to optimize your design to the smallest possible HW.

Good luck,

#### vaf20

##### Full Member level 3 hi again
does anyone know which algorithm be used by synthesizer to implement '*'(multiplier) if leave it free.or even '+'(adder)?
i would like to know what's the minimum threshold for implementation in the case of area optimization ?
tnx 4 ur help

#### vaf20

##### Full Member level 3 is there any method which is called serial IIR filter ?if so , let me know .
tnx

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