How will synthesized hardware look like?

[babaduredi]

Hi,
We have two scenarios:

module dff_blocking(d, clk, q)
input d,clk;
output q;
reg q,q1;
always@(posedge clk)
begin
q=d;
q1=q;
end
endmodule

and another one with non-blocking

module dff_nonblocking(d, clk, q)
input d,clk;
output q;
reg q,q1;
always@(posedge clk)
begin
q<=d;
q1<=q;
end
endmodule

How will the hardware look like in both cases post synthesis? second one looks simple but i don't have idea for first one.

 

[FvM]

I guess, the question is answered in nearly any Verilog tutorial discussing blocking versus nonblocking, e.g. the classical Cummings paper http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

Refer to "8.0 Pipeline modeling"

 

[mail4idle2]

Please find it attached.

 

[babaduredi]

Please find it attached.

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