i dnt know about sdf file,so pls tell me if Y<=a and b;
how to write sdf file for this and gate. and how can we give this file as input to modelsim simulator .pls help me.
sdf is standard delay format. I dont think you can do it without using timing analysis such as synopsys prime time or other tools. Google for it. Moreover, you have not assigned any delay to your non-blocking assignment statement OR there should be specification about the and gate delay which should be in the synthesis library.
Dont worry if this does not make sense. I am sure other knowledgeable friends will guide you further.