design_engineer
Newbie level 6
Hello,
I have a 17x14 signed multiplier (I use a * b) in my design which is implemented as a slow booth multiplier by the synthesis tool. However the gate count of this block is obviously very high. What ways do I have to reduce the gate count? I cannot use a serial multiplier because I do not have the clock cycles needed.
1. Does pipelining help reduce gate count? I currently use two clocks to multiply and latch the result. Can adding more cycles make the synthesizer optimize the gate counts? If so, do I add clock cycles to latch the result in more registers before finally using the result?
2. Can I break the 17x14 multiplier into two pieces (17x7) and use the same hardware block twice in two successive clocks and add the results (after applying the correct shifting). But since the operands are signed, this seems like it will not work because I am using a signed multiplier (ie., if I break the 14-bit operand into 7 bit operands (13:7), (6:0), it is possible that a '1' in bit 6 will cause the multiplication to be wrong because it will be viewed as a negative number). Any ideas on how this may be made to work?
Any other ideas?
Thanks.
I have a 17x14 signed multiplier (I use a * b) in my design which is implemented as a slow booth multiplier by the synthesis tool. However the gate count of this block is obviously very high. What ways do I have to reduce the gate count? I cannot use a serial multiplier because I do not have the clock cycles needed.
1. Does pipelining help reduce gate count? I currently use two clocks to multiply and latch the result. Can adding more cycles make the synthesizer optimize the gate counts? If so, do I add clock cycles to latch the result in more registers before finally using the result?
2. Can I break the 17x14 multiplier into two pieces (17x7) and use the same hardware block twice in two successive clocks and add the results (after applying the correct shifting). But since the operands are signed, this seems like it will not work because I am using a signed multiplier (ie., if I break the 14-bit operand into 7 bit operands (13:7), (6:0), it is possible that a '1' in bit 6 will cause the multiplication to be wrong because it will be viewed as a negative number). Any ideas on how this may be made to work?
Any other ideas?
Thanks.