sram bist verilog code
Mentor Mbistarchitecture is powerful tools to give memory bist logic in RTL format. It is readable.
You can design memory BIST circuit by a LFSR and PREG, It is two FSM. You can see any DFT book.
And you can refer synopsys DW_rambist about the memory bist arch.
For test algorithm and fault model, please search in IEEE or google. There are lots paper to say that.
Or you can see the book
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal Vlsi Circuits
by Michael J Bushnell, Vishwani D Agrawal