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How to implement Built In Self Test for RAM using verilog

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Feb 12, 2006
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implement memory verilog

Provided a verilog code is available for a RAM , how to go about writing a BIST code for the RAM.

how to implement ram in verilog

I know SRAM has some standard test algrithm . pls search google for this.
you can choose one to use.
and then implement it in RTL , do not forget to use a MUX to indicate a normal mode and a bist mode .

sram bist verilog

you have two ways :
1. using membist from mentor to do it , this tool is easy to use
2. find ip on opencore site.

sram bist verilog code

Mentor Mbistarchitecture is powerful tools to give memory bist logic in RTL format. It is readable.
You can design memory BIST circuit by a LFSR and PREG, It is two FSM. You can see any DFT book.
And you can refer synopsys DW_rambist about the memory bist arch.

For test algorithm and fault model, please search in IEEE or google. There are lots paper to say that.

Or you can see the book
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal Vlsi Circuits
by Michael J Bushnell, Vishwani D Agrawal

bist ram verilog

i hope BIST is generated using the tool you need not do manually

just go through the process guide of mbistarchitect

writetoknitin said:
Provided a verilog code is available for a RAM , how to go about writing a BIST code for the RAM.

sram tester verilog

1)the bist controller is generated by giving the memeory model as an input to the mbistarchitect tool
2)it generates bist controller,bist connection and testbench fiels.
3)now simulate this 3 files and the memory if test passes then its good if it fails just debug it.

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