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I know SRAM has some standard test algrithm . pls search google for this.
you can choose one to use.
and then implement it in RTL , do not forget to use a MUX to indicate a normal mode and a bist mode .
Mentor Mbistarchitecture is powerful tools to give memory bist logic in RTL format. It is readable.
You can design memory BIST circuit by a LFSR and PREG, It is two FSM. You can see any DFT book.
And you can refer synopsys DW_rambist about the memory bist arch.
For test algorithm and fault model, please search in IEEE or google. There are lots paper to say that.
Or you can see the book
Essentials of Electronic Testing for Digital, Memory, and Mixed-Signal Vlsi Circuits
by Michael J Bushnell, Vishwani D Agrawal
1)the bist controller is generated by giving the memeory model as an input to the mbistarchitect tool
2)it generates bist controller,bist connection and testbench fiels.
3)now simulate this 3 files and the memory if test passes then its good if it fails just debug it.