how to get timing report in SYNOPSYS PRIMETIME?

[amrithakrishnars]

I have a doubt with synopsys prime time regarding how to get timing report.In the following step how to give the clock pins(format for declaring input and output pins)

report_timing -from [all_registers -clock_pins] \
-to [all_registers -data_pins] -delay_type max \
-path_type full_clock –nosplit \
-max_paths 1 -nworst 1 \
-trans -cap -net > tc_reg2reg_setup.rpt

i am getting an error as path not found ,when i declare as below

report_timing -from DFFARX1 \rsr_out_reg[0]\.D(n10) -to \.Q(rsr_out[0])
report_timing -from DFFARX1 \rsr_out_reg[0]\.D(n10) .CLK(clock) .RSTB(n1) -to \.Q(rsr_out[0])
report_timing -from DFFARX1 \rsr_out_reg[0]\.D(n10) .CLK(clock) .RSTB(n1) -to .Q(rsr_out[0])


The netlist I got for my code is attached herewith.If possible please reply fast.I got stuck with my project because of this




module rsr ( clock, reset_rsr, enable_rsr, rsr_in, rsr_out );
input [7:0] rsr_in;
output [7:0] rsr_out;
input clock, reset_rsr, enable_rsr;
wire n10, n11, n12, n13, n14, n15, n16, n18, n1;

DFFARX1 \rsr_out_reg[7] ( .D(n18), .CLK(clock), .RSTB(n1), .Q(rsr_out[7])
);
DFFARX1 \rsr_out_reg[6] ( .D(n16), .CLK(clock), .RSTB(n1), .Q(rsr_out[6])
);
DFFARX1 \rsr_out_reg[5] ( .D(n15), .CLK(clock), .RSTB(n1), .Q(rsr_out[5])
);
DFFARX1 \rsr_out_reg[4] ( .D(n14), .CLK(clock), .RSTB(n1), .Q(rsr_out[4])
);
DFFARX1 \rsr_out_reg[3] ( .D(n13), .CLK(clock), .RSTB(n1), .Q(rsr_out[3])
);
DFFARX1 \rsr_out_reg[2] ( .D(n12), .CLK(clock), .RSTB(n1), .Q(rsr_out[2])
);
DFFARX1 \rsr_out_reg[1] ( .D(n11), .CLK(clock), .RSTB(n1), .Q(rsr_out[1])
);
DFFARX1 \rsr_out_reg[0] ( .D(n10), .CLK(clock), .RSTB(n1), .Q(rsr_out[0])
);
INVX0 U2 ( .INP(reset_rsr), .ZN(n1) );
MUX21X1 U3 ( .IN1(rsr_out[7]), .IN2(rsr_in[7]), .S(enable_rsr), .Q(n18) );
MUX21X1 U4 ( .IN1(rsr_out[6]), .IN2(rsr_in[6]), .S(enable_rsr), .Q(n16) );
MUX21X1 U5 ( .IN1(rsr_out[5]), .IN2(rsr_in[5]), .S(enable_rsr), .Q(n15) );
MUX21X1 U6 ( .IN1(rsr_out[4]), .IN2(rsr_in[4]), .S(enable_rsr), .Q(n14) );
MUX21X1 U7 ( .IN1(rsr_out[3]), .IN2(rsr_in[3]), .S(enable_rsr), .Q(n13) );
MUX21X1 U8 ( .IN1(rsr_out[2]), .IN2(rsr_in[2]), .S(enable_rsr), .Q(n12) );
MUX21X1 U9 ( .IN1(rsr_out[1]), .IN2(rsr_in[1]), .S(enable_rsr), .Q(n11) );
MUX21X1 U10 ( .IN1(rsr_out[0]), .IN2(rsr_in[0]), .S(enable_rsr), .Q(n10) );
endmodule


module adc_DW01_sub_0 ( A, B, CI, DIFF, CO );
input [7:0] A;
input [7:0] B;
output [7:0] DIFF;
input CI;
output CO;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9;
wire [8:0] carry;

FADDX1 U2_6 ( .A(A[6]), .B(n8), .CI(carry[6]), .CO(carry[7]), .S(DIFF[6]) );
FADDX1 U2_5 ( .A(A[5]), .B(n7), .CI(carry[5]), .CO(carry[6]), .S(DIFF[5]) );
FADDX1 U2_4 ( .A(A[4]), .B(n6), .CI(carry[4]), .CO(carry[5]), .S(DIFF[4]) );
FADDX1 U2_3 ( .A(A[3]), .B(n5), .CI(carry[3]), .CO(carry[4]), .S(DIFF[3]) );
FADDX1 U2_2 ( .A(A[2]), .B(n4), .CI(carry[2]), .CO(carry[3]), .S(DIFF[2]) );
FADDX1 U2_1 ( .A(A[1]), .B(n3), .CI(carry[1]), .CO(carry[2]), .S(DIFF[1]) );
XOR3X1 U2_7 ( .IN1(A[7]), .IN2(n9), .IN3(carry[7]), .Q(DIFF[7]) );
NAND2X1 U1 ( .IN1(B[0]), .IN2(n1), .QN(carry[1]) );
INVX0 U2 ( .INP(B[1]), .ZN(n3) );
INVX0 U3 ( .INP(B[2]), .ZN(n4) );
INVX0 U4 ( .INP(B[3]), .ZN(n5) );
INVX0 U5 ( .INP(B[4]), .ZN(n6) );
INVX0 U6 ( .INP(B[5]), .ZN(n7) );
INVX0 U7 ( .INP(B[6]), .ZN(n8) );
INVX0 U8 ( .INP(A[0]), .ZN(n1) );
INVX0 U9 ( .INP(B[0]), .ZN(n2) );
INVX0 U10 ( .INP(B[7]), .ZN(n9) );
XOR2X1 U11 ( .IN1(n1), .IN2(n2), .Q(DIFF[0]) );
endmodule


module adc ( sav, rsr_out, L3_in );
input [7:0] sav;
input [7:0] rsr_out;
output [7:0] L3_in;
wire \U1/U1/Z_0 , \U1/U1/Z_1 , \U1/U1/Z_2 , \U1/U1/Z_3 , \U1/U1/Z_4 ,
\U1/U1/Z_5 , \U1/U1/Z_6 , \U1/U1/Z_7 , \U1/U2/Z_0 , \U1/U2/Z_1 ,
\U1/U2/Z_2 , \U1/U2/Z_3 , \U1/U2/Z_4 , \U1/U2/Z_5 , \U1/U2/Z_6 ,
\U1/U2/Z_7 , n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n19;

adc_DW01_sub_0 r65 ( .A({\U1/U1/Z_7 , \U1/U1/Z_6 , \U1/U1/Z_5 , \U1/U1/Z_4 ,
\U1/U1/Z_3 , \U1/U1/Z_2 , \U1/U1/Z_1 , \U1/U1/Z_0 }), .B({\U1/U2/Z_7 ,
\U1/U2/Z_6 , \U1/U2/Z_5 , \U1/U2/Z_4 , \U1/U2/Z_3 , \U1/U2/Z_2 ,
\U1/U2/Z_1 , \U1/U2/Z_0 }), .CI(1'b0), .DIFF(L3_in) );
MUX21X1 U2 ( .IN1(rsr_out[7]), .IN2(sav[7]), .S(n1), .Q(\U1/U2/Z_7 ) );
MUX21X1 U3 ( .IN1(rsr_out[6]), .IN2(sav[6]), .S(n1), .Q(\U1/U2/Z_6 ) );
MUX21X1 U4 ( .IN1(rsr_out[5]), .IN2(sav[5]), .S(n1), .Q(\U1/U2/Z_5 ) );
MUX21X1 U5 ( .IN1(rsr_out[4]), .IN2(sav[4]), .S(n1), .Q(\U1/U2/Z_4 ) );
MUX21X1 U6 ( .IN1(rsr_out[3]), .IN2(sav[3]), .S(n1), .Q(\U1/U2/Z_3 ) );
MUX21X1 U7 ( .IN1(rsr_out[2]), .IN2(sav[2]), .S(n1), .Q(\U1/U2/Z_2 ) );
MUX21X1 U8 ( .IN1(rsr_out[1]), .IN2(sav[1]), .S(n1), .Q(\U1/U2/Z_1 ) );
MUX21X1 U9 ( .IN1(rsr_out[0]), .IN2(sav[0]), .S(n1), .Q(\U1/U2/Z_0 ) );
OR2X1 U10 ( .IN1(sav[7]), .IN2(rsr_out[7]), .Q(\U1/U1/Z_7 ) );
MUX21X1 U11 ( .IN1(sav[6]), .IN2(rsr_out[6]), .S(n1), .Q(\U1/U1/Z_6 ) );
MUX21X1 U12 ( .IN1(sav[5]), .IN2(rsr_out[5]), .S(n1), .Q(\U1/U1/Z_5 ) );
MUX21X1 U13 ( .IN1(sav[4]), .IN2(rsr_out[4]), .S(n1), .Q(\U1/U1/Z_4 ) );
MUX21X1 U14 ( .IN1(sav[3]), .IN2(rsr_out[3]), .S(n1), .Q(\U1/U1/Z_3 ) );
MUX21X1 U15 ( .IN1(sav[2]), .IN2(rsr_out[2]), .S(n1), .Q(\U1/U1/Z_2 ) );
MUX21X1 U16 ( .IN1(sav[1]), .IN2(rsr_out[1]), .S(n1), .Q(\U1/U1/Z_1 ) );
MUX21X1 U17 ( .IN1(sav[0]), .IN2(rsr_out[0]), .S(n1), .Q(\U1/U1/Z_0 ) );
AOI21X1 U18 ( .IN1(sav[7]), .IN2(n2), .IN3(n3), .QN(n1) );
OA22X1 U19 ( .IN1(sav[7]), .IN2(n2), .IN3(n4), .IN4(n5), .Q(n3) );
AND2X1 U20 ( .IN1(n6), .IN2(sav[6]), .Q(n5) );
OA221X1 U21 ( .IN1(sav[5]), .IN2(n7), .IN3(sav[6]), .IN4(n6), .IN5(n8), .Q(
n4) );
AO221X1 U22 ( .IN1(sav[4]), .IN2(n9), .IN3(sav[5]), .IN4(n7), .IN5(n10), .Q(
n8) );
OA221X1 U23 ( .IN1(sav[3]), .IN2(n11), .IN3(sav[4]), .IN4(n9), .IN5(n12),
.Q(n10) );
AO222X1 U24 ( .IN1(n13), .IN2(n14), .IN3(sav[2]), .IN4(n15), .IN5(sav[3]),
.IN6(n11), .Q(n12) );
NAND2X0 U25 ( .IN1(rsr_out[2]), .IN2(n16), .QN(n15) );
INVX0 U26 ( .INP(rsr_out[2]), .ZN(n14) );
INVX0 U27 ( .INP(n16), .ZN(n13) );
AO22X1 U28 ( .IN1(rsr_out[1]), .IN2(n17), .IN3(n18), .IN4(rsr_out[0]), .Q(
n16) );
OA21X1 U29 ( .IN1(rsr_out[1]), .IN2(n17), .IN3(n19), .Q(n18) );
INVX0 U30 ( .INP(sav[0]), .ZN(n19) );
INVX0 U31 ( .INP(sav[1]), .ZN(n17) );
INVX0 U32 ( .INP(rsr_out[3]), .ZN(n11) );
INVX0 U33 ( .INP(rsr_out[4]), .ZN(n9) );
INVX0 U34 ( .INP(rsr_out[6]), .ZN(n6) );
INVX0 U35 ( .INP(rsr_out[5]), .ZN(n7) );
INVX0 U36 ( .INP(rsr_out[7]), .ZN(n2) );
endmodule


module adder ( L3_out, adder_in, L1_in );
input [7:0] L3_out;
input [14:0] adder_in;
output [14:0] L1_in;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22;

XNOR2X1 U1 ( .IN1(adder_in[9]), .IN2(n1), .Q(L1_in[9]) );
NAND2X0 U2 ( .IN1(adder_in[8]), .IN2(n2), .QN(n1) );
XOR2X1 U3 ( .IN1(n2), .IN2(adder_in[8]), .Q(L1_in[8]) );
XOR3X1 U4 ( .IN1(adder_in[7]), .IN2(L3_out[7]), .IN3(n3), .Q(L1_in[7]) );
XOR3X1 U5 ( .IN1(adder_in[6]), .IN2(L3_out[6]), .IN3(n4), .Q(L1_in[6]) );
XOR3X1 U6 ( .IN1(adder_in[5]), .IN2(L3_out[5]), .IN3(n5), .Q(L1_in[5]) );
XOR3X1 U7 ( .IN1(adder_in[4]), .IN2(L3_out[4]), .IN3(n6), .Q(L1_in[4]) );
XOR3X1 U8 ( .IN1(adder_in[3]), .IN2(L3_out[3]), .IN3(n7), .Q(L1_in[3]) );
XOR3X1 U9 ( .IN1(adder_in[2]), .IN2(L3_out[2]), .IN3(n8), .Q(L1_in[2]) );
XOR3X1 U10 ( .IN1(adder_in[1]), .IN2(L3_out[1]), .IN3(n9), .Q(L1_in[1]) );
XOR2X1 U11 ( .IN1(adder_in[14]), .IN2(n10), .Q(L1_in[14]) );
NOR2X0 U12 ( .IN1(n11), .IN2(n12), .QN(n10) );
XOR2X1 U13 ( .IN1(n12), .IN2(n11), .Q(L1_in[13]) );
NAND2X0 U14 ( .IN1(adder_in[12]), .IN2(n13), .QN(n11) );
INVX0 U15 ( .INP(adder_in[13]), .ZN(n12) );
XOR2X1 U16 ( .IN1(adder_in[12]), .IN2(n13), .Q(L1_in[12]) );
AND3X1 U17 ( .IN1(adder_in[10]), .IN2(n14), .IN3(adder_in[11]), .Q(n13) );
XOR2X1 U18 ( .IN1(adder_in[11]), .IN2(n15), .Q(L1_in[11]) );
AND2X1 U19 ( .IN1(n14), .IN2(adder_in[10]), .Q(n15) );
XOR2X1 U20 ( .IN1(adder_in[10]), .IN2(n14), .Q(L1_in[10]) );
AND3X1 U21 ( .IN1(adder_in[8]), .IN2(n2), .IN3(adder_in[9]), .Q(n14) );
AO22X1 U22 ( .IN1(L3_out[7]), .IN2(n3), .IN3(adder_in[7]), .IN4(n16), .Q(n2)
);
OR2X1 U23 ( .IN1(n3), .IN2(L3_out[7]), .Q(n16) );
AO22X1 U24 ( .IN1(L3_out[6]), .IN2(n4), .IN3(adder_in[6]), .IN4(n17), .Q(n3)
);
OR2X1 U25 ( .IN1(n4), .IN2(L3_out[6]), .Q(n17) );
AO22X1 U26 ( .IN1(L3_out[5]), .IN2(n5), .IN3(adder_in[5]), .IN4(n18), .Q(n4)
);
OR2X1 U27 ( .IN1(n5), .IN2(L3_out[5]), .Q(n18) );
AO22X1 U28 ( .IN1(L3_out[4]), .IN2(n6), .IN3(adder_in[4]), .IN4(n19), .Q(n5)
);
OR2X1 U29 ( .IN1(n6), .IN2(L3_out[4]), .Q(n19) );
AO22X1 U30 ( .IN1(L3_out[3]), .IN2(n7), .IN3(adder_in[3]), .IN4(n20), .Q(n6)
);
OR2X1 U31 ( .IN1(n7), .IN2(L3_out[3]), .Q(n20) );
AO22X1 U32 ( .IN1(L3_out[2]), .IN2(n8), .IN3(adder_in[2]), .IN4(n21), .Q(n7)
);
OR2X1 U33 ( .IN1(n8), .IN2(L3_out[2]), .Q(n21) );
AO22X1 U34 ( .IN1(L3_out[1]), .IN2(n9), .IN3(adder_in[1]), .IN4(n22), .Q(n8)
);
OR2X1 U35 ( .IN1(L3_out[1]), .IN2(n9), .Q(n22) );
AND2X1 U36 ( .IN1(adder_in[0]), .IN2(L3_out[0]), .Q(n9) );
XOR2X1 U37 ( .IN1(adder_in[0]), .IN2(L3_out[0]), .Q(L1_in[0]) );
endmodule


module L2_L3_0 ( sav, L2_L3_out, clock, reset );
input [7:0] sav;
output [7:0] L2_L3_out;
input clock, reset;
wire n8;

DFFARX1 \L2_L3_out_reg[7] ( .D(sav[7]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[7]) );
DFFARX1 \L2_L3_out_reg[6] ( .D(sav[6]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[6]) );
DFFARX1 \L2_L3_out_reg[5] ( .D(sav[5]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[5]) );
DFFARX1 \L2_L3_out_reg[4] ( .D(sav[4]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[4]) );
DFFARX1 \L2_L3_out_reg[3] ( .D(sav[3]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[3]) );
DFFARX1 \L2_L3_out_reg[2] ( .D(sav[2]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[2]) );
DFFARX1 \L2_L3_out_reg[1] ( .D(sav[1]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[1]) );
DFFARX1 \L2_L3_out_reg[0] ( .D(sav[0]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[0]) );
INVX0 U3 ( .INP(reset), .ZN(n8) );
endmodule


module L2_L3_1 ( sav, L2_L3_out, clock, reset );
input [7:0] sav;
output [7:0] L2_L3_out;
input clock, reset;
wire n8;

DFFARX1 \L2_L3_out_reg[7] ( .D(sav[7]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[7]) );
DFFARX1 \L2_L3_out_reg[6] ( .D(sav[6]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[6]) );
DFFARX1 \L2_L3_out_reg[5] ( .D(sav[5]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[5]) );
DFFARX1 \L2_L3_out_reg[4] ( .D(sav[4]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[4]) );
DFFARX1 \L2_L3_out_reg[3] ( .D(sav[3]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[3]) );
DFFARX1 \L2_L3_out_reg[2] ( .D(sav[2]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[2]) );
DFFARX1 \L2_L3_out_reg[1] ( .D(sav[1]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[1]) );
DFFARX1 \L2_L3_out_reg[0] ( .D(sav[0]), .CLK(clock), .RSTB(n8), .Q(
L2_L3_out[0]) );
INVX0 U3 ( .INP(reset), .ZN(n8) );
endmodule


module L1 ( L1_in, L1_out, clock, reset );
input [14:0] L1_in;
output [14:0] L1_out;
input clock, reset;
wire n15;

DFFARX1 \L1_out_reg[14] ( .D(L1_in[14]), .CLK(clock), .RSTB(n15), .Q(
L1_out[14]) );
DFFARX1 \L1_out_reg[13] ( .D(L1_in[13]), .CLK(clock), .RSTB(n15), .Q(
L1_out[13]) );
DFFARX1 \L1_out_reg[12] ( .D(L1_in[12]), .CLK(clock), .RSTB(n15), .Q(
L1_out[12]) );
DFFARX1 \L1_out_reg[11] ( .D(L1_in[11]), .CLK(clock), .RSTB(n15), .Q(
L1_out[11]) );
DFFARX1 \L1_out_reg[10] ( .D(L1_in[10]), .CLK(clock), .RSTB(n15), .Q(
L1_out[10]) );
DFFARX1 \L1_out_reg[9] ( .D(L1_in[9]), .CLK(clock), .RSTB(n15), .Q(
L1_out[9]) );
DFFARX1 \L1_out_reg[8] ( .D(L1_in[8]), .CLK(clock), .RSTB(n15), .Q(
L1_out[8]) );
DFFARX1 \L1_out_reg[7] ( .D(L1_in[7]), .CLK(clock), .RSTB(n15), .Q(
L1_out[7]) );
DFFARX1 \L1_out_reg[6] ( .D(L1_in[6]), .CLK(clock), .RSTB(n15), .Q(
L1_out[6]) );
DFFARX1 \L1_out_reg[5] ( .D(L1_in[5]), .CLK(clock), .RSTB(n15), .Q(
L1_out[5]) );
DFFARX1 \L1_out_reg[4] ( .D(L1_in[4]), .CLK(clock), .RSTB(n15), .Q(
L1_out[4]) );
DFFARX1 \L1_out_reg[3] ( .D(L1_in[3]), .CLK(clock), .RSTB(n15), .Q(
L1_out[3]) );
DFFARX1 \L1_out_reg[2] ( .D(L1_in[2]), .CLK(clock), .RSTB(n15), .Q(
L1_out[2]) );
DFFARX1 \L1_out_reg[1] ( .D(L1_in[1]), .CLK(clock), .RSTB(n15), .Q(
L1_out[1]) );
DFFARX1 \L1_out_reg[0] ( .D(L1_in[0]), .CLK(clock), .RSTB(n15), .Q(
L1_out[0]) );
INVX2 U3 ( .INP(reset), .ZN(n15) );
endmodule

top module


module PE ( clock, reset, en, rsr_in, sav_in, rsr_out, sav_out, adder_in,
adder_out );
input [7:0] rsr_in;
input [7:0] sav_in;
output [7:0] rsr_out;
output [7:0] sav_out;
input [14:0] adder_in;
output [14:0] adder_out;
input clock, reset, en;

wire [7:0] L3_in;
wire [7:0] L3_out;
wire [14:0] L1_in;

rsr r1 ( .clock(clock), .reset_rsr(reset), .enable_rsr(en), .rsr_in(rsr_in),
.rsr_out(rsr_out) );
adc a1 ( .sav(sav_in), .rsr_out(rsr_out), .L3_in(L3_in) );
adder a2 ( .L3_out(L3_out), .adder_in(adder_in), .L1_in(adder_out) );
L2_L3_0 L2 ( .sav(sav_in), .L2_L3_out(sav_out), .clock(clock), .reset(reset)
);
L2_L3_1 L3 ( .sav(L3_in), .L2_L3_out(L3_out), .clock(clock), .reset(reset)
);
L1 a3 ( .L1_in({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), .clock(clock), .reset(reset) );
endmodule

 

[tariq786]

I think you should change this

report_timing -from [all_registers -clock_pins] \
-to [all_registers -data_pins] -delay_type max \

to
report_timing -from [all_registers -clock_pins] \
-to [all_registers -Qoutputs] -delay_type max \


Note that i am not sure of the syntax. You should change the Qoutputs to make sure that you plug in Q output of the register according to the syntax.

Try this and let us know

 

[Alosevskoy]

Hello!

Timing report about setup times for all registers:
report_timing -to [all_registers -data_pins]

Timing report about hold times for all registers:
report_timing -to [all_registers -data_pins] -delay_type min

Timing report about setup time for a particular register (for example \rsr_out_reg[7] register in r1 cell):
report_timing -to r1/rsr_out_reg[7]/D
(!note that the backslash "\" in the register name was omitted)

My previous post was entirely wrong :smile:

Good luck!

 

[matter]

I agree with both the ideas from Tariq and Alosevskoy.
My suggestion is
1.) Make sure that you can see the pins or ports from your pt_shell. i.e. do a get_pins DFFARX1 \rsr_out_reg[0]\.D(n10) and get_pin \.Q(rsr_out[0]).
If you find errors here, then fix them accordingly.

2.) Since you mentioned that the error message you are getting is about path not found, I am assuming that you got the pin names correct. Otherwise you would get pin not found error message.
So try using the -through switch instead of -from/-to i.e. use
report_timing -through xyz -through abc

3.) If you still don't get a timing report, my guess is that this path is not getting clocked. check your constraints and make sure that clocks are reaching the flops.

---------- Post added at 22:44 ---------- Previous post was at 22:41 ----------

Along with checking for clocks in #3 above, if these are I/O paths make sure that you are constraining the path with proper set_input/output_delay commands.