How to get cascaded clocks information at synthesis level

[dianin]

Can anybody tells how to get cascaded clock information at the synthesis level?

Cascaded clocks are the master clocks which are defined at the fanout of another master clock. For example design have two clocks one is CLK1 at top-level and CLK2 which is defined at hierarchical level but is the fanout of CLK1 ; then during CTS, tool tries to balace flip-flops (clocked by CLK1) with clock-source cell for CLK2, this causes the large skew (if it is clockinf the 1000 of flip-flops) .Most of the time it is difficult to debug timing violations if the designs have multiple clocks and large skew issues.

I think solution is to, set exclude pin at the souce pin of CLK2 during CTS, or remove the clock defintion CLK2 and use only CLK1, but the question is how to get the cascaded clock information to apply above solution , especially for big design (SoC level)? If we get information at the early stge of design , it will save lot of time. Please let me know if anybody have any suggetion.

Best Regards

 

[lostinxlation]

Are you defining CLK2 as a generated clock with a source point CLK1 or as an independent clock ?
if CLK2 was defined as a generated clock, the tool shouldn't try to balance the CLK1 and CLK2.

 

[rca]

Encounter CTS goes through the generated clock, and used only the create_clock has clock source.
In generate my design have 10k flipflop from on clock source and the skew is correctly handle, and I prefer only one clock source to symplify my clock tree and the scan insertion.

 

[dianin]

CLK2 is not generated clock, it is another master clock.

 

[lostinxlation]

Then just exclude the pin with CLK2 or take off CLK2 definition( I still don't know why it is not generated_clock when the second clock is within a fanout of another clock or why just not use CLK1).

Answering your question how to get the information for cascaded clocks...... I don't know what to say, to be honest. Whoever made clock definitions has to know where to define the clocks, and he is in charge of knowing all those information. The most troublesome task on top level design of ASIC chips is clock definition since ASIC ususally has very comlicated clocking scheme. If whoever in charge of clock definition can't provide that info, the project could go really bad.

However, if you write a script, you shold be able to find the cascaded case by yourself. For example, you report all the instance belonging to a fanout starting at some clock on STA tool (like report_transitive_fanout or such on PT) and compare them with all the clock definition points reported by the STA tool(may be report_clock). If an instance matches, that's a cascaded clock. It should be a very simple perl script.

 

[sameer_dlh25]

Why it should be master clock at hierarchal level ?
It means you do not want to balance hierarchal sync pins with top level sync pins. Is it OK :-|

 

[dianin]

Thanks for inputs.

I agree that whoever in charge of clock definitiop should know the clock structure properly. But with script , can catch clock related issue quickly.

 

[aravind]

u can create clock at the port where another clock also present. use create_generated_clock -add -master_clock...
Then tool will treat new clock as clock root point..
best of luck

 

[Kaisia]

Are you defining CLK2 as a generated clock with a source point CLK1 or as an independent clock ?
if CLK2 was defined as a generated clock, the tool shouldn't try to balance the CLK1 and CLK2.

do you mean the backend tool (for example encounter) identify the generated clock by means of 'throughpins' statement in clock.ctstch?
and it will not make any balance between CLK1 and CLK2.

in my opinion, the tool will do balance them. any idea?