dianin
Member level 2
Can anybody tells how to get cascaded clock information at the synthesis level?
Cascaded clocks are the master clocks which are defined at the fanout of another master clock. For example design have two clocks one is CLK1 at top-level and CLK2 which is defined at hierarchical level but is the fanout of CLK1 ; then during CTS, tool tries to balace flip-flops (clocked by CLK1) with clock-source cell for CLK2, this causes the large skew (if it is clockinf the 1000 of flip-flops) .Most of the time it is difficult to debug timing violations if the designs have multiple clocks and large skew issues.
I think solution is to, set exclude pin at the souce pin of CLK2 during CTS, or remove the clock defintion CLK2 and use only CLK1, but the question is how to get the cascaded clock information to apply above solution , especially for big design (SoC level)? If we get information at the early stge of design , it will save lot of time. Please let me know if anybody have any suggetion.
Best Regards
Cascaded clocks are the master clocks which are defined at the fanout of another master clock. For example design have two clocks one is CLK1 at top-level and CLK2 which is defined at hierarchical level but is the fanout of CLK1 ; then during CTS, tool tries to balace flip-flops (clocked by CLK1) with clock-source cell for CLK2, this causes the large skew (if it is clockinf the 1000 of flip-flops) .Most of the time it is difficult to debug timing violations if the designs have multiple clocks and large skew issues.
I think solution is to, set exclude pin at the souce pin of CLK2 during CTS, or remove the clock defintion CLK2 and use only CLK1, but the question is how to get the cascaded clock information to apply above solution , especially for big design (SoC level)? If we get information at the early stge of design , it will save lot of time. Please let me know if anybody have any suggetion.
Best Regards