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How to design this circuit?

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shaq

shaq

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Hello everyone,

My question is listed in following figure.

ω is gate delay of three inverters.

Can anyone tell me how to implement it to achieve the output?
 

see below link, it may helpful
 
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Dear Davood Amerion,

Thank you for your help!

Now, my idea is that CLK connects to 3 inverters and output signal I called it "Delay clk".

Finally, the result of CLK xor Delay clk is output.

Does anyone has any suggestion?
 

chip is 4 2NAND logic

Sorry for ugly writing i just erased ORCAD for clean install
 

artem said:
chip is 4 2NAND logic

Sorry for ugly writing i just erased ORCAD for clean install
Click to expand...

Dear artem,

What does the other pin of 1st 2NAND logic connect to ?
 

second and first are connected together to form inverter - that is my fault.
 

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