Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How to design this circuit?

Status
Not open for further replies.

shaq

Full Member level 5
Joined
Jul 23, 2005
Messages
312
Helped
14
Reputation
28
Reaction score
4
Trophy points
1,298
Activity points
3,397
Hello everyone,

My question is listed in following figure.

ω is gate delay of three inverters.

Can anyone tell me how to implement it to achieve the output?
 

Davood Amerion

Advanced Member level 2
Joined
Mar 1, 2005
Messages
584
Helped
116
Reputation
232
Reaction score
24
Trophy points
1,298
Location
Persia
Activity points
6,345
see below link, it may helpful
 
Last edited by a moderator:

shaq

Full Member level 5
Joined
Jul 23, 2005
Messages
312
Helped
14
Reputation
28
Reaction score
4
Trophy points
1,298
Activity points
3,397
Dear Davood Amerion,

Thank you for your help!

Now, my idea is that CLK connects to 3 inverters and output signal I called it "Delay clk".

Finally, the result of CLK xor Delay clk is output.

Does anyone has any suggestion?
 

artem

Advanced Member level 4
Joined
May 22, 2003
Messages
1,350
Helped
126
Reputation
252
Reaction score
32
Trophy points
1,328
Location
Turkey
Activity points
13,450
chip is 4 2NAND logic

Sorry for ugly writing i just erased ORCAD for clean install
 

shaq

Full Member level 5
Joined
Jul 23, 2005
Messages
312
Helped
14
Reputation
28
Reaction score
4
Trophy points
1,298
Activity points
3,397
artem said:
chip is 4 2NAND logic

Sorry for ugly writing i just erased ORCAD for clean install

Dear artem,

What does the other pin of 1st 2NAND logic connect to ?
 

artem

Advanced Member level 4
Joined
May 22, 2003
Messages
1,350
Helped
126
Reputation
252
Reaction score
32
Trophy points
1,328
Location
Turkey
Activity points
13,450
second and first are connected together to form inverter - that is my fault.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top