sicetn
Newbie

Assuming that after I configure the sequential circuit with DFT, I need to write a STIL file to input my test patterns to simulate the fault coverage,but the STIL file need procedure of "capture_clk" or "load_unload" and so on, making file writing and simulation processes more complex.At the same time,in the pattern block, there are more complex pattern inputs than in the combination circuit,which confusing me.So are there any cases or manuals here that can solve my doubts?
Thanks
Thanks