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How to create a bypass model for AU faults seen in DFT coverage test?

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badola

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Hi all,

In my design i have pll, cpu and embedded memories as black box. I am generating the stuckat reconfigure patterns using fastscan. I am loosing some 4.13% covergae because of black boxes only. This coverage loss is because of AU faults. I checked one AU fault, it is showing that the fault before the black box in not observed at the output. I have some 24k scan cells in my design. After pattern generation i am getting 17k AU faults. Now the issue is if i try to add observe point at each Au fault then my area is increasing almost twice. Can anyone suggest me how should i create a bypass model for faults for bypassing the black boxes. I am usinf DFT compiler for scan insertion and Design Compiler for synthesis. I am using set_test_point_element command for adding the observe point. Please suggest where should and how should i make the bypass logic.
Looking forward for help from u guys.
Thanks in advance.

sudhanshu
 

HolySaint

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dft test coverage

can u give your drc report with violations?
 

sunilbudumuru

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site:www.edaboard.com dft

Hello Friend,

Insert test point elebents (both observe and control points) around the RAMs and CPU (be acreful of analog nodes/ports of CPU if any). Do not touch PLL.

Test points will work to improve coverage. But inserting the TPs at right location is very important.

If u insert TPs, they will take care of bypassing the logic.

asic-dft.com
Sunil Budumuru
 

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