How to avoid DFF whose input D is connected to 1'b0 or 1'b1 in Design Compiler?

[watersong]

I always get some DFFs whose input D is connected to 1'b0 or 1'b1 after I finish logic synthesis via Design Compiler. Is there any way to avoid such a case, for example, any commands in Design Compiler? I really appreciate that if anyone would like to help me deal with this problem. I am looking forward to replys:razz:

 

[lostinxlation]

Check the value of compile_seqmap_propagate_constants and compile_delete_unloaded_sequential_cells with printvar command.

 

[watersong]

Thank you so much for your reply! I will try it right away!

---------- Post added at 14:53 ---------- Previous post was at 14:39 ----------

I checked the value of the two variables, both of them are "true". -_-!!

 

[lostinxlation]

weird..
Did you not see any message saying the flops are removed in the log file ?
Or are these flops settale or resettable where the set or reset value is different from the value during normal operation ??
Or are these flops already stiched in the scan chain ?

 

[watersong]

There are some msg in log file saying that certain registers are constant and will be removed. And they are removed indeed at the end. But there are still some constant DFFs not appearing in the log but appearing in the final netlist. These DFFs are not in a scan chain. Actually it is a design without scan insertion. Don't quite understand the meaning of your second question. Sorry and thank you so much!

 

[lostinxlation]

it suggests that there are some reasons that those specific registers cannot be removed.
Are these registers with reset or set pins ? What's the value on D input.

 

[watersong]

Yes, you are right. All these registers have both set and reset. The value on D input depends on the value of Reset and Set. If Reset input of register is 1'b1, Set input of register is !reset(here reset is the top level input signal), then D input of that register is 1'b0; if Set input of register is 1'b1, Reset input of register is !reset, then D input of that register is 1'b1. When the Reset of a register is 0, the output is 1. When the Set of a register is 0, the output is 0.

it suggests that there are some reasons that those specific registers cannot be removed.
Are these registers with reset or set pins ? What's the value on D input.

 

[lostinxlation]

That explains why DC didn't remove them.

Even though D input is 0, DC cannot remove it if that flop can be 1 due to set signal. The same is true for a resettable flop with D=1.

 

[watersong]

Does that mean this kind of registers are unavoidable? What if I remove the reset network?

That explains why DC didn't remove them.

Even though D input is 0, DC cannot remove it if that flop can be 1 due to set signal. The same is true for a resettable flop with D=1.

 

[lostinxlation]

It depends on the logic.
If you need to initialize the register to a certain value to start up the chip, and need that register to hold a different value after boot sequence is completed, you can't avoid such a flop. However, I believe you can make the logic in a way to work around such a condition. Frankly, I don't think there should be many registers like those(may be a few in a chip is reasoable, I guess).
More likely scenario is the set/reset pin in those registers are synchronous. If so, that's just a different way to make a logic, so you can't work around.

 

[watersong]

Thank you so much! I will think about it.

It depends on the logic.
If you need to initialize the register to a certain value to start up the chip, and need that register to hold a different value after boot sequence is completed, you can't avoid such a flop. However, I believe you can make the logic in a way to work around such a condition. Frankly, I don't think there should be many registers like those(may be a few in a chip is reasoable, I guess).
More likely scenario is the set/reset pin in those registers are synchronous. If so, that's just a different way to make a logic, so you can't work around.