zero wireload model
Thanks!
Here, I have a .25 TSMC standard cell library, which can't auto select the wire-load model as needed, I have no idear of which one I should choose from the following when I synthesis my design for the first time and I don't know the estimated gates of it. What should I do? And then what should I base my desicion on? What does the name of "smic18_wl10","smic18_wl20" and so on refer to? Thanks!
/* wire-loads */
wire_load("smic18_wl10") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 66.667;
fanout_length (1,66.667);
}
wire_load("smic18_wl20") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 133.334;
fanout_length (1,133.334);
}
wire_load("smic18_wl30") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 200.001;
fanout_length (1,200.001);
}
wire_load("smic18_wl40") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 266.668;
fanout_length (1,266.668);
}
wire_load("smic18_wl50") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 333.335;
fanout_length (1,333.335);
}
/* QA wire-load */
wire_load("ForQA") {
resistance : 0;
capacitance : 1;
area : 1;
slope : 1;
fanout_length(1,0);
fanout_length(10,0);
}
/* additional header data */
default_wire_load : "TSMC25_Conservative";
default_wire_load_mode : segmented;