how interconnect length depends on fanout

[tybhsl]

wire load model

when i try to use design compiler to synthesis my code, I dont know what is wire_load and which one I should choose in thelibrary. I need your help, Thank you very much!

 

[floatgrass]

wireload model

let tools automatical select.
or estimate your gate number ,then select a model from your db lib.

 

[wadaye]

zero wire load model

Hi,

Now most Fab's library don't have area based select option. So you need to

assign one. It's depend your optimism degree.

 

[tybhsl]

zero wireload model

Thanks!
Here, I have a .25 TSMC standard cell library, which can't auto select the wire-load model as needed, I have no idear of which one I should choose from the following when I synthesis my design for the first time and I don't know the estimated gates of it. What should I do? And then what should I base my desicion on? What does the name of "smic18_wl10","smic18_wl20" and so on refer to? Thanks!

/* wire-loads */
wire_load("smic18_wl10") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 66.667;
fanout_length (1,66.667);
}
wire_load("smic18_wl20") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 133.334;
fanout_length (1,133.334);
}
wire_load("smic18_wl30") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 200.001;
fanout_length (1,200.001);
}
wire_load("smic18_wl40") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 266.668;
fanout_length (1,266.668);
}
wire_load("smic18_wl50") {
resistance : 8.5e-8;
capacitance : 1.5e-4;
area : 0.7;
slope : 333.335;
fanout_length (1,333.335);
}
/* QA wire-load */
wire_load("ForQA") {
resistance : 0;
capacitance : 1;
area : 1;
slope : 1;
fanout_length(1,0);
fanout_length(10,0);
}
/* additional header data */

default_wire_load : "TSMC25_Conservative";
default_wire_load_mode : segmented;

 

[hahaguy2]

wire load has zero net area

A wire load model is an estimate of a net’s RC parasitics based on the net’s fanout:

 

[sarath51]

wire_load slope

usually the library vendor provides a set of models and have to pick up one,

 

[giggs11]

forqa wire load

hi,

i had the same problem some time ago. The wire load model is an estimation of the wire length of the design. As layout has been achieved through P&R at the synthesis stage, the wiring length estimation has to be made.

Anyway, the wire load model has to be chosen on the following criteria; chip area and experience. I too hate it when senior designers say that experience will tell you the proper model to be chosen but for now just select based on area.

The models in my library kit are specified according to design dimension. but i'm not sure what urs represents. I posted the same query, so do look for my post to see the feedback i got.

Good luck.

 

[jinruan]

smic18_wl50

use report_lib command in DC and you will find the result

 

[wilfwolf]

design compiler wire load model

A wire load model is a table for estimating the capacitance,resistance and area of a net. It is based on a statistical correlation between net fanout and net length

 

[AlexWan]

wire load lib slope

Hi,

Hope the document have the information you need!

<Advance Chip Synthesis> Unit 1 PDF file:

 

[ecijun]

wire load liberary slope

I think, "smic18_wl10" represents the area of the chip is 10x10.

 

[spauls]

auto wire load

Search in DC Guide,
acyually it is net RC delay on wire.

 

[sazjad]

Re: auto wire load

Search in DC Guide,
acyually it is net RC delay on wire.

Can anyone send me ( or give link) some files of Design Compiler User Guide for doing Synthesis and STA. I have the tool , but i don't have the tutorial/documents.

Specially i want something good to learn synthesis scripting and how to write SDC file and all those things to complete the synthesis flow.

IF you have something please post here or here is my email address: sazjad@gmail.com

Thanks
sazzad

 

[vikadik]

I think the library that you are using is a smic 180nm ( smic18_10wl) not TSMC. For synthesis, just let the tool select a default one, unless you are using Design Compiler -topographical( Please check the website of Synopsys for topographical) which needs different files called the tluPlus( usually derived from ITF using STAR to calculate the RC capacitance. If you are using design compiler without topographical, then you need not worry about the wireload as ICCompiler will take care of wire load (parasatics) while doing a layout. It will add buffers as needed to compensate the parasatic and fanin and fanout loads.

---------- Post added at 23:27 ---------- Previous post was at 23:24 ----------

sazzad,

Please login to solvnet.synospys.com. You will find the details there and tutorials.